Datasheet

REV. C
ADSP-21065L
–35–
JTAG Test Access Port and Emulation
Parameter Min Max Unit
Timing Requirements:
t
TCK
TCK Period t
CK
ns
t
STAP
TDI, TMS Setup Before TCK High 3.0 ns
t
HTAP
TDI, TMS Hold After TCK High 3.0 ns
t
SSYS
System Inputs Setup Before TCK Low
1
7.0 ns
t
HSYS
System Inputs Hold After TCK Low
1
12.0 ns
t
TRSTW
TRST Pulsewidth 4 t
CK
ns
Switching Characteristics:
t
DTDO
TDO Delay from TCK Low 11.0 ns
t
DSYS
System Outputs Delay After TCK Low
2
15.0 ns
NOTES
1
System Inputs = DATA
31-0
, ADDR
23-0
, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR
1
, DMAR
2
, BR
2-1
, ID
1-0
, IRQ
2-0
, FLAG
11-0
, DR0x, DR1x, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BSEL, BMS, CLKIN, RESET, SDCLK
0
, RAS , CAS, SDWE, SDCKE, PWM_EVENTx.
2
System Outputs = DATA
31-0
, ADDR
23-0
, MS
3-0
, RD, WR, ACK, SW, HBG, REDY, DMAG1
,
DMAG2, BR
2-1
, CPA, FLAG
11-0
, PWM_EVENTx, DT0x, DT1x,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, SDCLK0, SDCLK1, DQM, SDA10, RAS, CAS , SDWE, SDCKE, BM, XTAL.
TCK
t
STAP
t
TCK
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
Figure 23. JTAG Test Access Port and Emulation