Datasheet

REV. C
ADSP-21065L
–32–
Serial Ports
Parameter Min Max Unit
External Clock
Timing Requirements:
t
SFSE
TFS/RFS Setup Before TCLK/RCLK
1
4.0 ns
t
HFSE
TFS/RFS Hold After TCLK/RCLK
1
4.0 ns
t
SDRE
Receive Data Setup Before RCLK
1
1.5 ns
t
HDRE
Receive Data Hold After RCLK
1
4.0 ns
t
SCLKW
TCLK/RCLK Width 9.0 ns
t
SCLK
TCLK/RCLK Period t
CK
ns
Internal Clock
Timing Requirements:
t
SFSI
TFS Setup Before TCLK
2
; RFS Setup Before RCLK
1
8.0 ns
t
HFSI
TFS/RFS Hold After TCLK/RCLK
1
1.0 ns
t
SDRI
Receive Data Setup Before RCLK
1
3.0 ns
t
HDRI
Receive Data Hold After RCLK
1
3.0 ns
External or Internal Clock
Switching Characteristics:
t
DFSE
RFS Delay After RCLK (Internally Generated RFS)
2
13.0 ns
t
HOFSE
RFS Hold After RCLK (Internally Generated RFS)
2
3.0 ns
External Clock
Switching Characteristics:
t
DFSE
TFS Delay After TCLK (Internally Generated TFS)
2
13.0 ns
t
HOFSE
TFS Hold After TCLK (Internally Generated TFS)
2
3.0 ns
t
DDTE
Transmit Data Delay After TCLK
2
12.5 ns
t
HDTE
Transmit Data Hold After TCLK
2
4.0 ns
Internal Clock
Switching Characteristics:
t
DFSI
TFS Delay After TCLK (Internally Generated TFS)
2
4.5 ns
t
HOFSI
TFS Hold After TCLK (Internally Generated TFS)
2
–1.5 ns
t
DDTI
Transmit Data Delay After TCLK
2
7.5 ns
t
HDTI
Transmit Data Hold After TCLK
2
0.0 ns
t
SCLKIW
TCLK/RCLK Width (t
SCLK
/2) – 2.5 (t
SCLK
/2) + 2.5 ns
Enable and Three-State
Switching Characteristics:
t
DTENE
Data Enable from External TCLK
2
5.0 ns
t
DDTTE
Data Disable from External RCLK
2
10.0 ns
t
DTENI
Data Enable from Internal TCLK
2
0.0 ns
t
DDTTI
Data Disable from Internal TCLK
2
3.0 ns
t
DCLK
TCLK/RCLK Delay from CLKIN 18.0 + 6 DT ns
t
DPTR
SPORT Disable After CLKIN 14.0 ns
External Late Frame Sync
t
DDTLFSE
Data Delay from Late External TFS or External RFS
with MCE = 1, MFD = 0
3, 4
10.5 ns
t
DTENLFSE
Data Enable from late FS or MCE = 1, MFD = 0
3, 4
3.5 ns
t
DDTLSCK
Data Delay from TCLK/RCLK for Late External
TFS or External RFS with MCE = 1, MFD = 0
3, 4
12.0 ns
t
DTENLSCK
Data Enable from RCLK/TCLK for Late External FS or
MCE = 1, MFD = 0
3, 4
4.5 ns
NOTES
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.
1
Referenced to sample edge.
2
Referenced to drive edge.
3
MCE = 1, TFS enable and TFS valid follow t
DDTENFS
and t
DDTLFSE.
4
If external RFS/TFS setup to RCLK/TCLK > t
SCLK
/2 then t
DDTLSCK
and t
DTENLSCK
apply; otherwise t
DDTLFSE
and t
DTENLFS
apply.
*Word selected timing for I
2
S mode is the same as TFS/RFS timing (normal framing only).