Datasheet

REV. C
ADSP-21065L
–30–
SDRAM Interface—Bus Master
Use these specifications for ADSP-21065L bus master accesses of SDRAM.
Parameter Min Max Unit
Timing Requirements:
t
SDSDK
Data Setup Before SDCLK 2.0 ns
t
HDSDK
Data Hold After SDCLK 1.25 ns
Switching Characteristics:
t
DSDK1
First SDCLK Rise Delay After CLKIN 9.0 + 6 DT 12.75 + 6 DT ns
t
DSDK2
Second SDCLK Rise Delay After CLKIN 25.5 + 22 DT 29.25 + 22 DT ns
t
SDK
SDCLK Period 16.67 t
CK
/2 ns
t
SDKH
SDCLK Width High 7.5 + 8 DT ns
t
SDKL
SDCLK Width Low 6.5 + 8 DT ns
t
DCADSDK
Command, Address, Data, Delay After SDCLK
1
10.0 + 5 DT ns
t
HCADSDK
Command, Address, Data, Hold After SDCLK
1
4.5 + 5 DT ns
t
SDTRSDK
Data Three-State After SDCLK 9.5 + 5 DT ns
t
SDENSDK
Data Enable After SDCLK
2
6.0 + 5 DT ns
t
SDCTR
SDCLK, Command Three-State After CLKIN
1
5.0 + 3 DT 9.75 + 3 DT ns
t
SDCEN
SDCLK, Command Enable After CLKIN
1
5.0 + 2 DT 10.0 + 2 DT ns
t
SDATR
Address Three-State After CLKIN –1.0 – 4 DT 3.0 – 4 DT ns
t
SDAEN
Address Enable After CLKIN 1.0 – 2 DT 7.0 – 2 DT ns
NOTES
1
Command = SDCKE, MSx, RAS, CAS , SDWE, DQM, and SDA10.
2
SDRAM controller adds one SDRAM CLK three-stated cycle delay (t
CK
/2) on a Read followed by a Write.
SDRAM Interface—Bus Slave
These timing requirements allow a bus slave to sample the bus master’s SDRAM command and detect when a refresh occurs.
Parameter Min Max Unit
Timing Requirements:
t
SSDKC1
First SDCLK Rise After CLKIN 6.50 + 16 DT 17.5 + 16 DT ns
t
SSDKC2
Second SDCLK Rise After CLKIN 23.25 34.25 ns
t
SCSDK
Command Setup Before SDCLK* 0.0 ns
t
HCSDK
Command Hold After SDCLK* 2.0 ns
NOTE
*Command = SDCKE, RAS, CAS , and SDWE.