Datasheet

REV. C
ADSP-21065L
–28–
DMA Handshake
These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled
by the ADDR
23-0
, RD, WR, SW , MS
3-0
, ACK, and DMAG signals. External mode cannot be used for transfers with SDRAM. For
Paced Master mode, the data transfer is controlled by ADDR
23-0
, RD, WR, MS
3-0
, and ACK (not DMAG). For Paced Master mode,
the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for
ADDR
23-0
, RD, WR, MS
3-0
, SW, DATA
31-0
, and ACK also apply.
Parameter Min Max Unit
Timing Requirements:
t
SDRLC
DMARx Low Setup Before CLKIN
1
5.0 ns
t
SDRHC
DMARx High Setup Before CLKIN
1
5.0 ns
t
WDR
DMARx Width Low (Nonsynchronous) 6.0 ns
t
SDATDGL
Data Setup After DMAGx Low
2
15.0 + 20 DT ns
t
HDATIDG
Data Hold After DMAGx High 0.0 ns
t
DATDRH
Data Valid After DMARx High
2
25.0 + 14 DT ns
t
DMARLL
DMARx Low Edge to Low Edge 18.0 + 14 DT ns
t
DMARH
DMARx Width High 6.0 ns
Switching Characteristics:
t
DDGL
DMAGx Low Delay After CLKIN 14.0 + 10 DT 20.0 + 10 DT ns
t
WDGH
DMAGx High Width 10.0 + 12 DT + HI ns
t
WDGL
DMAGx Low Width 16.0 + 20 DT ns
t
HDGC
DMAGx High Delay After CLKIN 0.0 – 2 DT 6.0 – 2 DT ns
t
DADGH
Address Select Valid to DMAGx High 28.0 + 16 DT ns
t
DDGHA
Address Select Hold After DMAGx High –1.0 ns
t
VDATDGH
Data Valid Before DMAGx High
3
16.0 + 20 DT ns
t
DATRDGH
Data Disable After DMAGx High
4
0.0 4.0 ns
t
DGWRL
WR Low Before DMAGx Low 5.0 + 6 DT 8.0 + 6 DT ns
t
DGWRH
DMAGx Low Before WR High 18.0 + 19 DT + W ns
t
DGWRR
WR High Before DMAGx High 0.75 + 1 DT 3.0 + 1 DT ns
t
DGRDL
RD Low Before DMAGx Low 5.0 8.0 ns
t
DRDGH
RD Low Before DMAGx High 24.0 + 26 DT + W ns
t
DGRDR
RD High Before DMAGx High 0.0 2.0 ns
t
DGWR
DMAGx High to WR, RD Low 5.0 + 6 DT + HI ns
W = (number of wait states specified in WAIT register) ¥ t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1
Only required for recognition in the current cycle.
2
t
SDATDGL
is the data setup requirement if DMAR x is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven t
DATDRH
after DMARx is brought high.
3
t
VDATDGH
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t
VDATDGH
= 8 + 9 DT + (n ¥ t
CK
) where n
equals the number of extra cycles that the access is prolonged.
4
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.