Datasheet

REV. C
ADSP-21065L
–26–
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and
the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin.
Parameter Min Max Unit
Timing Requirements:
t
STSCK
SBTS Setup Before CLKIN 7.0 + 8 DT ns
t
HTSCK
SBTS Hold Before CLKIN 1.0 + 8 DT ns
Switching Characteristics:
t
MIENA
Address/Select Enable After CLKIN 1.0 – 2 DT ns
t
MIENS
Strobes Enable After CLKIN
1
–0.5 – 2 DT ns
t
MIENHG
HBG Enable After CLKIN 2.0 – 2 DT ns
t
MITRA
Address/Select Disable After CLKIN 3.0 – 4 DT ns
t
MITRS
Strobes Disable After CLKIN
1
4.0 – 4 DT ns
t
MITRHG
HBG Disable After CLKIN 5.5 – 4 DT ns
t
DATEN
Data Enable After CLKIN
2
10.0 + 5 DT ns
t
DATTR
Data Disable After CLKIN
2
1.0 – 2 DT 7.0 – 2 DT ns
t
ACKEN
ACK Enable After CLKIN
2
7.5 + 4 DT ns
t
ACKTR
ACK Disable After CLKIN
2
1.0 – 2 DT 6.0 – 2 DT ns
t
MTRHBG
Memory Interface Disable Before HBG Low
3
2.0 + 2 DT ns
t
MENHBG
Memory Interface Enable After HBG High
3
15.75 + DT ns
NOTES
1
Strobes = RD, WR, SW, DMAG.
2
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address, RD, WR, MS x, SW, DMAGx, BMS (in EPROM boot mode).