Datasheet

REV. C
ADSP-21065L
–24–
Asynchronous Read/Write—Host to ADSP-21065L
Use these specifications for asynchronous host processor accesses of an ADSP-21065L, after the host has asserted CS and HBR
(low). After the ADSP-21065L returns HBG, the host can drive the RD and WR pins to access the ADSP-21065L’s IOP registers.
HBR and HBG are assumed low for this timing. Writes can occur at a minimum interval of (1/2) t
CK
.
Parameter Min Max Unit
Read Cycle
Timing Requirements:
t
SADRDL
Address Setup
/
CS Low Before RD Low* 0.0 ns
t
HADRDH
Address Hold/CS Hold Low After RD High 0.0 ns
t
WRWH
RD/WR High Width 6.0 ns
t
DRDHRDY
RD High Delay After REDY (O/D) Disable 0.0 ns
t
DRDHRDY
RD High Delay After REDY (A/D) Disable 0.0 ns
Switching Characteristics:
t
SDATRDY
Data Valid Before REDY Disable from Low 1.5 ns
t
DRDYRDL
REDY (O/D) or (A/D) Low Delay After RD Low 13.5 ns
t
RDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read 28.0 + DT ns
t
HDARWH
Data Disable After RD High 2.0 10.0 ns
Write Cycle
Timing Requirements:
t
SCSWRL
CS Low Setup Before WR Low 0.0 ns
t
HCSWRH
CS Low Hold After WR High 0.0 ns
t
SADWRH
Address Setup Before WR High 5.0 ns
t
HADWRH
Address Hold After WR High 2.0 ns
t
WWRL
WR Low Width 7.0 ns
t
WRWH
RD/WR High Width 6.0 ns
t
DWRHRDY
WR High Delay After REDY (O/D) or (A/D) Disable 0.0 ns
t
SDATWH
Data Setup Before WR High 5.0 ns
t
HDATWH
Data Hold After WR High 1.0 ns
Switching Characteristics:
t
DRDYWRL
REDY (O/D) or (A/D) Low Delay After WR/CS Low 13.5 ns
t
RDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write 7.75 ns
NOTE
*Not required if RD and address are valid t
HBGRCSV
after HBG goes low. For first access after HBR asserted, ADDR23-0 must be a nonMMS value 1/2 t
CLK
before
RD or WR goes low or by t
HBGRCSV
after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See Host Inter-
face, in the ADSP-21065L SHARC User’s Manual, Second Edition.