Datasheet

REV. C
ADSP-21065L
–22–
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between multiprocessing ADSP-21065Ls (BRx) or a host processor (HBR,
HBG).
Parameter Min Max Unit
Timing Requirements:
t
HBGRCSV
HBG Low to RD/WR/CS Valid
1
20.0 + 36 DT ns
t
SHBRI
HBR Setup Before CLKIN
2
12.0 + 12 DT ns
t
HHBRI
HBR Hold Before CLKIN
2
6.0 + 12 DT ns
t
SHBGI
HBG Setup Before CLKIN 6.0 + 8 DT ns
t
HHBGI
HBG Hold Before CLKIN High 1.0 + 8 DT ns
t
SBRI
BRx, CPA Setup Before CLKIN
3
7.0 + 8 DT ns
t
HBRI
BRx, CPA Hold Before CLKIN High 1.0 + 8 DT ns
Switching Characteristics:
t
DHBGO
HBG Delay After CLKIN 8.0 – 2 DT ns
t
HHBGO
HBG Hold After CLKIN 1.0 – 2 DT ns
t
DBRO
BRx Delay After CLKIN 7.0 – 2 DT ns
t
HBRO
BRx Hold After CLKIN 1.0 – 2 DT ns
t
DCPAO
CPA Low Delay After CLKIN 11.5 – 2 DT ns
t
TRCPA
CPA Disable After CLKIN 1.0 – 2 DT 5.5 – 2 DT ns
t
DRDYCS
REDY (O/D) or (A/D) Low from CS and HBR Low
4
13.0 ns
t
TRDYHG
REDY (O/D) Disable or REDY (A/D) High from HBG
4
44.0 + 43 DT ns
t
ARDYTR
REDY (A/D) Disable from CS or HBR High
4
10.0 ns
NOTES
1
For first asynchronous access after HBR and CS asserted, ADDR
23-0
must be a nonMMS value 1/2 t
CK
before RD or WR goes low or by t
HBGRCSV
after HBG goes
low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Processor Control of the ADSP-21065L section of the
ADSP-21065L SHARC User’s Manual, Second Edition.
2
Only required for recognition in the current cycle.
3
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4
(O/D) = open drain, (A/D) = active drive.