Datasheet

REV. C
ADSP-21065L
–20–
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21065L bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave) timing requirements.
Parameter Min Max Unit
Timing Requirements:
t
SADRI
Address, SW Setup Before CLKIN 24.5 + 25 DT ns
t
HADRI
Address, SW Hold Before CLKIN 4.0 + 8 DT ns
t
SRWLI
RD/WR Low Setup Before CLKIN
1
21.0 + 21 DT ns
t
HRWLI
RD/WR Low Hold After CLKIN –2.50 – 5 DT 7.5 + 7 DT ns
t
RWHPI
RD/WR Pulse High 2.5 ns
t
SDATWH
Data Setup Before WR High 4.5 ns
t
HDATWH
Data Hold After WR High 0.0 ns
Switching Characteristics:
t
SDDATO
Data Delay After CLKIN 31.75 + 21 DT ns
t
DATTR
Data Disable After CLKIN
2
1.0 – 2 DT 7.0 – 2 DT ns
t
DACK
ACK Delay After CLKIN 29.5 + 20 DT ns
t
ACKTR
ACK Disable After CLKIN
2
1.0 – 2 DT 6.0 – 2 DT ns
NOTES
1
t
SRWLI
is specified when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t
SRWLI
(min) = 17.5 + 18 DT.
2
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
For two ADSP-21065Ls to communicate synchronously as master and slave, certain master and slave specification combinations
must be satisfied. Do not compare specification values directly to calculate master/slave clock skew margins for those specifications
listed below. The following table shows the appropriate clock skew margin.
Table IV. Bus Master to Slave Skew Margins
Master Specification Slave Specification Skew Margin
t
SSDATI
t
SDDATO
t
CK
= 33.3 ns + 2.25 ns
t
CK
= 30.0 ns + 1.50 ns
t
SACKC
t
DACK
t
CK
= 33.3 ns + 3.00 ns
t
CK
= 30.0 ns + 2.25 ns
t
DADRO
t
SADRI
t
CK
= 33.3 ns N/A
t
CK
= 30.0 ns + 2.75 ns
t
DRWL
(Max) t
SRWLI
t
CK
= 33.3 ns + 1.50 ns
t
CK
= 30.0 ns + 1.25 ns
t
DRDO
(Max) t
HRWLI
(Max) t
CK
= 33.3 ns N/A
t
CK
= 30.0 ns 3.00 ns
t
DWRO
(Max) t
HRWLI
(Max) t
CK
= 33.3 ns N/A
t
CK
= 30.0 ns 3.75 ns