Datasheet

REV. C
ADSP-21065L
–18–
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN-relative timing or for accessing a slave
ADSP-21065L (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous
memory reads and writes (see Memory Read—Bus Master and Memory Write—Bus Master).
When accessing a slave ADSP-21065L, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-21065L must also meet these (bus master) timing require-
ments for data and acknowledge setup and hold times.
Parameter Min Max Unit
Timing Requirements:
t
SSDATI
Data Setup Before CLKIN 0.25 + 2 DT ns
t
HSDATI
Data Hold After CLKIN 4.0 – 2 DT ns
t
DAAK
ACK Delay After Address, MSx, SW, BMS
1, 2
24.0 + 30 DT + W ns
t
SACKC
ACK Setup Before CLKIN
1
2.75 + 4 DT ns
t
HACK
ACK Hold After CLKIN 2.0 – 4 DT ns
Switching Characteristics:
t
DADRO
Address, MSx, BMS, SW Delay After CLKIN
1
7.0 – 2 DT ns
t
HADRO
Address, MSx, BMS, SW Hold After CLKIN 0.5 – 2 DT ns
t
DRDO
RD High Delay After CLKIN 0.5 – 2 DT 6.0 – 2 DT ns
t
DWRO
WR High Delay After CLKIN 0.0 – 3 DT 6.0 – 3 DT ns
t
DRWL
RD/WR Low Delay After CLKIN 7.5 + 4 DT 11.75 + 4 DT ns
t
DDATO
Data Delay After CLKIN 22.0 + 10 DT ns
t
DATTR
Data Disable After CLKIN
3
1.0 – 2 DT 7.0 – 2 DT ns
t
DBM
BMSTR Delay After CLKIN 3.0 ns
t
HBM
BMSTR Hold After CLKIN –4.0 ns
W = (number of wait states specified in WAIT register) ¥ t
CK
.
NOTES
1
Data Hold: User must meet t
HDA
or t
HDRH
or synchronous specification t
HDATI
. See system hold time calculation under test conditions for the calculation of hold
times given capacitive and dc loads.
2
ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by t
DAAK
or t
DSAK
or synchronous specification t
SACKC
for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications t
SACKC
and t
HACKC
must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.