Datasheet

REV. C
ADSP-21065L
–17–
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these
timing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin
timing requirements as described in the note below.
Parameter Min Max Unit
Timing Requirements:
t
DAAK
ACK Delay from Address
1, 2
24.0 + 30 DT + W ns
t
DSAK
ACK Delay from WR Low
1
19.5 + 24 DT + W ns
Switching Characteristics:
t
DAWH
Address, Selects to WR Deasserted
2
29.0 + 31 DT + W ns
t
DAWL
Address, Selects to WR Low
2
3.5 + 6 DT ns
t
WW
WR Pulsewidth 24.5 + 25 DT + W ns
t
DDWH
Data Setup Before WR High 15.5 + 19 DT + W ns
t
DWHA
Address Hold After WR Deasserted 0.0 + 1 DT + H ns
t
DATRWH
Data Disable After WR Deasserted
3
1.0 + 1 DT + H 4.0 + 1 DT + H ns
t
WWR
WR High to WR, RD Low 4.5 + 7 DT + H ns
t
WRDGL
WR High to DMAGx Low 11.0 + 13 DT + H ns
t
DDWR
Data Disable Before WR or RD Low 3.5 + 6 DT + I ns
t
WDE
WR Low to Data Enabled 4.5 + 6 DT ns
W = (number of wait states specified in WAIT register) ¥ t
CK
.
H = t
CK
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = t
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTES
1
ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by t
DAAK
or t
DSAK
or synchronous specification t
SACKC
for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications t
SACKC
and t
HACKC
must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).
2
The falling edge of MSx, SW, and BMS is referenced.
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
RD
ACK
DATA
WR
ADDRESS
MSx , SW
BMS
t
DAWL
t
WW
t
DAAK
t
WWR
t
WDE
t
DDWR
t
DWHA
t
DDWH
t
DAWH
t
DSAK
DMAG
t
DATRWH
t
WRDGL
Figure 12. Memory Write—Bus Master