Datasheet

REV. C
ADSP-21065L
–16–
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these
timing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin
timing requirements as described in the note below.
Parameter Min Max Unit
Timing Requirements:
t
DAD
Address, Selects Delay to Data Valid
1, 2
28.0 + 32 DT + W ns
t
DRLD
RD Low to Data Valid
1
24.0 + 26 DT + W ns
t
HDA
Data Hold from Address Selects
3
0.0 ns
t
HDRH
Data Hold from RD High
3
0.0 ns
t
DAAK
ACK Delay from Address, Selects
2, 3
24.0 + 30 DT + W ns
t
DSAK
ACK Delay from RD Low
3
19.5 + 24 DT + W ns
Switching Characteristics:
t
DRHA
Address, Selects Hold After RD High –1.0 + H ns
t
DARL
Address, Selects to RD Low
2
3.0 + 6 DT ns
t
RW
RD Pulsewidth 25.0 + 26 DT + W ns
t
RWR
RD High to WR, RD Low 4.5 + 6 DT + HI ns
t
RDGL
RD High to DMAGx Low 11.0 +12 DT + HI ns
W = (number of wait states specified in WAIT register) ¥ t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1
Data Delay/Setup: User must meet t
DAD
or to t
DRLD
or synchronous specification t
SSDATI
.
2
The falling edge of MS x, SW, BMS, are referenced.
3
ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by t
DAAK
or t
DSAK
or synchronous specification t
SACKC
for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications t
SACKC
and t
HACKC
must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).
WR
ACK
DATA
RD
ADDRESS
MSx , SW
BMS
t
DARL
t
RW
t
DAAK
t
RWR
t
DRHA
t
DSAK
DMAG
t
HDRH
t
RDGL
t
DRLD
t
DAD
t
HDA
Figure 11. Memory Read—Bus Master