Datasheet

REV. C
ADSP-21065L
–14–
Switching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor
will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device con-
nected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read opera-
tion. Timing requirements guarantee that the processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
66 MHz 60 MHz
Parameter Min Max Min Max Unit
Clock Input
Timing Requirements:
t
CK
CLKIN Period 30.00 100 33.33 100 ns
t
CKL
CLKIN Width Low 7.0 7.0 ns
t
CKH
CLKIN Width High 5.0 5.0 ns
t
CKRF
CLKIN Rise/Fall (0.4 V–2.0 V) 3.0 3.0 ns
CLKIN
t
CKH
t
CK
t
CKL
Figure 7. Clock Input
Parameter Min Max Unit
Reset
Timing Requirements:
t
WRST
RESET Pulsewidth Low
1
2 t
CK
ns
t
SRST
RESET Setup Before CLKIN High
2
23.5 + 24 DT t
CK
ns
NOTES
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 3000 CLKIN cycles while RESET is
low, assuming stable V
DD
and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after
reset.
CLKIN
RESET
t
WRST
t
SRST
Figure 8. Reset
Parameter Min Max Unit
Interrupts
Timing Requirements:
t
SIR
IRQ2-0 Setup Before CLKIN High or Low
1
11.0 + 12 DT ns
t
HIR
IRQ2-0 Hold Before CLKIN High or Low
1
0.0 + 12 DT ns
t
IPW
IRQ2-0 Pulsewidth
2
2.0 + t
CK
/2 ns
NOTES
1
Only required for IRQx recognition in the following cycle.
2
Applies only if t
SIR
and t
HIR
requirements are not met.