Datasheet

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F | Page 21 of 64 | March 2008
ESD CAUTION
PACKAGE MARKING INFORMATION
Figure 8 and Table 8 provide information on detail contained
within the package marking for the ADSP-2106x processors
(actual marking format may vary). For a complete listing of
product availability, see Ordering Guide on Page 61.
TIMING SPECIFICATIONS
The ADSP-2106x processors are available at maximum proces-
sor speeds of 33 MHz (–133), and 40 MHz (–160). The timing
specifications are based on a CLKIN frequency of 40 MHz
t
CK
= 25 ns). The DT derating factor enables the calculation for
timing specifications within the min to max range of the t
CK
specification (see Table 9). DT is the difference between the der-
ated CLKIN period and a CLKIN period of 25 ns:
DT = t
CK
– 25 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, you
cannot meaningfully add parameters to derive longer times.
For voltage reference levels, see Figure 28 on Page 47 under Test
Conditions.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices. (O/D) = Open Drain,
(A/D) = Active Drive.
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Figure 8. Typical Package Brand
Table 8. Package Brand Information
Brand Key Field Description
t Temperature Range
pp Package Type
Z Lead (Pb) Free Option
ccc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
yyww Date Code
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid
performance degradation or loss of functionality.
vvvvvv.x n.n
tppZccc
S
ADSP-2106x
a
yyww country_of_origin