Datasheet

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F | Page 5 of 64 | March 2008
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-2106x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With its separate program and data
memory buses and on-chip instruction cache, the processor can
simultaneously fetch two
operands and an instruction (from the
cache), all in a single cycle.
Instruction Cache
The ADSP-2106x includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-2106x’s two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-2106x contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any mem-
ory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of
parallel operations, for concise programming. For example, the
ADSP-2106x can conditionally execute a multiply, an add, a
subtract and a branch, all in a single instruction.
MEMORY AND I/O INTERFACE FEATURES
The ADSP-2106x processors add the following architectural
features to the SHARC family core.
Dual-Ported On-Chip Memory
The ADSP-21062/ADSP-21062L contains two megabits of on-
chip SRAM, and the ADSP-21060/ADSP-21060L contains
4M bits of on-chip SRAM. The internal memory is organized as
two equal sized blocks of 1M bit each for the ADSP-21062/
ADSP-21062L and two equal sized blocks of 2M bits each for
the ADSP-21060/ADSP-21060L. Each can be configured for dif-
ferent combinations of code and data storage. Each memory
block is dual-ported for single-cycle, independent accesses by
the core processor and I/O processor or DMA controller. The
dual-ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle.
On the ADSP-21062/ADSP-21062L, the memory can be config-
ured as a maximum of 64k words of 32-bit data, 128k words of
16-bit data, 40k words of 48-bit instructions (or 40-bit data), or
combinations of different word sizes up to two megabits. All of
the memory can be accessed as 16-bit, 32-bit, or 48-bit words.
On the ADSP-21060/ADSP-21060L, the memory can be config-
ured as a maximum of 128k words of 32-bit data, 256k words of
16-bit data, 80k words of 48-bit instructions (or 40-bit data), or
combinations of different word sizes up to four megabits. All of
the memory can be accessed as 16-bit, 32-bit or 48-bit words.
A 16-bit floating-point storage format is supported, which effec-
tively doubles the amount of data that can be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit float-
ing-point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the
ADSP-2106x’s external port.
On-Chip Memory and Peripherals Interface
The ADSP-2106x’s external port provides the processor’s inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-2106x’s unified
address space. The separate on-chip buses—for PM addresses,
PM data, DM addresses, DM data, I/O addresses, and I/O
data—are multiplexed at the external port to create an external
system bus with a single 32-bit address bus and a single 48-bit
(or 32-bit) data bus.
Addressing of external memory devices is facilitated by on-chip
decoding of high-order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-2106x
provides programmable memory wait states and external mem-
ory acknowledge controls to allow interfacing to DRAM and
peripherals with variable access, hold and disable time
requirements.
Host Processor Interface
The ADSP-2106x’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with lit-
tle additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-2106x’s exter-
nal port and is memory-mapped into the unified address space.
Four channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead.
The host processor requests the ADSP-2106x’s external bus with
the host bus request (HBR
), host bus grant (HBG), and ready
(REDY) signals. The host can directly read and write the inter-
nal memory of the ADSP-2106x, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.