Datasheet

Rev. F | Page 2 of 64 | March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
PROCESSOR FEATURES (Continued)
The processor family provides a variety of features. For a com-
parison across family members, see Table 1.
PARALLEL COMPUTATIONS
Single-cycle multiply and ALU operations in parallel with
dual memory read/writes and instruction fetch
Multiply with add and subtract for accelerated FFT butterfly
computation
UP TO 4M BIT ON-CHIP SRAM
Dual-ported for independent access by core processor and
DMA
OFF-CHIP MEMORY INTERFACING
4 gigawords addressable
Programmable wait state generation, page-mode DRAM
support
DMA CONTROLLER
10 DMA channels for transfers between ADSP-2106x internal
memory and external memory, external peripherals, host
processor, serial ports, or link ports
Background DMA transfers at up to 40 MHz, in parallel with
full-speed processor execution
HOST PROCESSOR INTERFACE TO 16- AND 32-BIT
MICROPROCESSORS
Host can directly read/write ADSP-2106x internal memory
and IOP registers
MULTIPROCESSING
Glueless connection for scalable DSP multiprocessing
architecture
Distributed on-chip bus arbitration for parallel bus connect
of up to six ADSP-2106xs plus host
6 link ports for point-to-point connectivity and array
multiprocessing
240 MBps transfer rate over parallel bus
240 MBps transfer rate over link ports
SERIAL PORTS
Two 40 Mbps synchronous serial ports with companding
hardware
Independent transmit and receive functions
Table 1. ADSP-2106x SHARC Processor Family Features
Feature ADSP-21060 ADSP-21062 ADSP-21060L ADSP-21062L ADSP-21060C ADSP-21060LC
SRAM 4M bits 2M bits 4M bits 2M bits 4M bits 4M bits
Operating
Voltage
5 V 5 V 3.3 V 3.3 V 5 V 3.3 V
Instruction
Rate
33 MHz
40 MHz
33 MHz
40 MHz
33 MHz
40 MHz
33 MHz
40 MHz
33 MHz
40 MHz
33 MHz
40 MHz
Package MQFP_PQ4
PBGA
MQFP_PQ4
PBGA
MQFP_PQ4
PBGA
MQFP_PQ4
PBGA
CQFP CQFP