Datasheet

Rev. F | Page 16 of 64 | March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
INTERNAL POWER DISSIPATION (5 V)
These specifications apply to the internal power portion of V
DD
only. For a complete discussion of the code used to measure
power dissipation, see the technical note “SHARC Power Dissi-
pation Measurements.”
Specifications are based on the operating scenarios.
To estimate power consumption for a specific application, use
the following equation where % is the amount of time your pro-
gram spends in that state:
%PEAK I
DDINPEAK
+%HIGH I
DDINHIGH
+%LOW I
DDINLOW
+
%IDLE I
DDIDLE
= Power Consumption
Operation Peak Activity (I
DDINPEAK
) High Activity (I
DDINHIGH
) Low Activity (I
DDINLOW
)
Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None
Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles
Parameter Test Conditions Max Units
I
DDINPEAK
Supply Current (Internal)
1
t
CK
= 30 ns, V
DD
= Max
t
CK
= 25 ns, V
DD
= Max
745
850
mA
mA
I
DDINHIGH
Supply Current (Internal)
2
t
CK
= 30 ns, V
DD
= Max
t
CK
= 25 ns, V
DD
= Max
575
670
mA
mA
I
DDINLOW
Supply Current (Internal)
2
t
CK
= 30 ns, V
DD
= Max
t
CK
= 25 ns, V
DD
= Max
340
390
mA
mA
I
DDIDLE
Supply Current (Idle)
3
V
DD
= Max 200 mA
1
The test program used to measure I
DDINPEAK
represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power
measurements made using typical applications are less than specified.
2
I
DDINHIGH
is a composite average based on a range of high activity code. I
DDINLOW
is a composite average based on a range of low activity code.
3
Idle denotes ADSP-2106x state during execution of IDLE instruction.