Datasheet

ADSP-21061/ADSP-21061L
Rev. D | Page 39 of 52 | May 2013
Table 25. Serial Ports—Internal Clock
Parameter
5 V and 3.3 V
Unit
Min Max
Switching Characteristics
t
DFSI
TFS Delay After TCLK (Internally Generated TFS)
1
4.5 ns
t
HOFSI
TFS Hold After TCLK (Internally Generated TFS)
1
–1.5 ns
t
DDTI
Transmit Data Delay After TCLK
1
7.5 ns
t
HDTI
Transmit Data Hold After TCLK
1
0ns
t
SCLKIW
TCLK/RCLK Width t
SCLK
/2 –1.5 t
SCLK
/2+1.5 ns
1
Referenced to drive edge.
Table 26. Serial Ports—Enable and Three-State
Parameter
5 V and 3.3 V
Unit
Min Max
Switching Characteristics
t
DDTEN
Data Enable from External TCLK
1, 2
4.5 ns
t
DDTTE
Data Disable from External TCLK
1
10.5 ns
t
DDTIN
Data Enable from Internal TCLK
1
0ns
t
DDTTI
Data Disable from Internal TCLK
1
3ns
t
DCLK
TCLK/RCLK Delay from CLKIN 22 + 3DT/8 ns
t
DPTR
SPORT Disable After CLKIN 17 ns
1
Referenced to drive edge.
2
For the ADSP-21061L (3.3 V), this specification is 3.5 ns min.
Table 27. Serial Ports—External Late Frame Sync
Parameter
5 V and 3.3 V
Unit
Min Max
Switching Characteristics
t
DDTLFSE
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0
1
12 ns
t
DDTENFS
Data Enable from Late FS or MCE = 1, MFD = 0
1
3.5 ns
1
MCE = 1, TFS enable and TFS valid follow t
DDTLFSE
and t
DDTENFS
.