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Microcontrollers, Microprocessors & Quartzes
Digital signal processor (DSP) MQFP 240 EP (32x32) 3.3 V 44 MHz
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ADSP-21061
/
ADSP-21061L
Rev
. D
|
Page 35
of 52
|
May 2013
Figure 22.
Three-State Timing
(Bus
Transition Cycle, SBTS
Assertion)
MEMOR
Y
INTERFACE
HBG
MEMORY IN
TERFACE = ADDRE
SS
,
RD
,
WR
,
MSx
,
SW
,P
A
G
E
,
DMAGx
.
BMS
(IN EPROM BOOT MODE)
t
MENHBG
t
MTRHBG
1
...
...
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