Datasheet

Rev. D | Page 32 of 52 | May 2013
ADSP-21061/ADSP-21061L
Asynchronous Read/Write—Host to ADSP-21061
Use these specifications for asynchronous host processor
accesses of an ADSP-21061, after the host has asserted CS
and
HBR
(low). After HBG is returned by the ADSP-21061, the host
can drive the RD
and WR pins to access the ADSP-21061’s
internal memory or IOP registers. HBR
and HBG are assumed
low for this timing.
Table 17. Read Cycle
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SADRDL
Address Setup/CS Low Before RD Low
1
0ns
t
HADRDH
Address Hold/CS Hold Low After RD 0ns
t
WRWH
RD/WR High Width 6 ns
t
DRDHRDY
RD High Delay After REDY (O/D) Disable 0 ns
t
DRDHRDY
RD High Delay After REDY (A/D) Disable 0 ns
Switching Characteristics
t
SDATRDY
Data Valid Before REDY Disable from Low 2 ns
t
DRDYRDL
REDY (O/D) or (A/D) Low Delay After RD Low
2
10 ns
t
RDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read 45 + DT ns
t
HDARWH
Data Disable After RD High 2 8 ns
1
Not required if RD and address are valid t
HBGRCSV
after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 t
CLK
before RD or WR goes
low or by t
HBGRCSV
after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the
ADSP-21061” section in the ADSP-2106x SHARC User’s Manual.
2
For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.
Table 18. Write Cycle
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SCSWRL
CS Low Setup Before WR Low 0 ns
t
HCSWRH
CS Low Hold After WR High 0 ns
t
SADWRH
Address Setup Before WR High 5 ns
t
HADWRH
Address Hold After WR High 2 ns
t
WWRL
WR Low Width 8 ns
t
WRWH
RD/WR High Width 6 ns
t
DWRHRDY
WR High Delay After REDY (O/D) or (A/D) Disable 0 ns
t
SDATWH
Data Setup Before WR High
50 MHz, t
CK
= 20 ns
1
3
2.5
ns
t
HDATWH
Data Hold After WR High 1 ns
Switching Characteristics
t
DRDYWRL
REDY (O/D) or (A/D) Low Delay After WR/CS Low
2
11 ns
t
RDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write 15 ns
t
SRDYCK
REDY (O/D) or (A/D) Disable to CLKIN 1 + 7DT/16 8 + 7DT/16 ns
1
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t
CK
< 25 ns. For all other devices, use the preceding timing specification of the same name.
2
For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.