Datasheet

Rev. D | Page 28 of 52 | May 2013
ADSP-21061/ADSP-21061L
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21061 bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave)
timing requirements.
Table 15. Synchronous Read/Write—Bus Slave
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SADRI
Address, SW Setup Before CLKIN 14 + DT/2 ns
t
HADRI
Address, SW Hold After CLKIN 5 + DT/2 ns
t
SRWLI
RD/WR Low Setup Before CLKIN
1
8.5 + 5DT/16 ns
t
HRWLI
RD/WR Low Hold After CLKIN
44 MHz/50 MHz
2
–4 – 5DT/16
–3.5 – 5DT/16
8 + 7DT/16
8 + 7DT/16
ns
t
RWHPI
RD/WR Pulse High 3 ns
t
SDATWH
Data Setup Before WR High 3 ns
t
HDATWH
Data Hold After WR High 1 ns
Switching Characteristics
t
SDDATO
Data Delay After CLKIN 19 + 5DT/16 ns
t
DATTR
Data Disable After CLKIN
3
0 – DT/8 7 – DT/8 ns
t
DACKAD
ACK Delay After Address, SW
4
8ns
t
ACKTR
ACK Disable After CLKIN
2
–1 – DT/8 6 – DT/8 ns
1
t
SRWLI
(min) = 9.5 + 5DT/16 when multiprocessor memory space wait state (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t
SRWLI
(min)= 4 + DT/8.
2
This specification applies to the ADSP-21061LKS-176 (3.3 V, 44 MHz) and the ADSP-21061KS-200 (5 V, 50 MHz), operating at t
CK
< 25 ns. For all other devices, use the
preceding timing specification of the same name.
3
See Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.
4
t
DACKAD
is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and inputs have setup
times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of
the state of MMSWS or strobes. A slave will three-state ACK every cycle with t
ACKTR
.