Datasheet

ADSP-21061/ADSP-21061L
Rev. D | Page 21 of 52 | May 2013
Clock Input
Reset
Table 7. Clock Input
Parameter
ADSP-21061
50 MHz, 5 V
ADSP-21061L
44 MHz, 3.3 V
ADSP-21061/
ADSP-21061L
40 MHz,
5 V and 3.3 V
ADSP-21061
33 MHz, 5 V
UnitMin Max Min Max Min Max Min Max
Timing Requirements
t
CK
CLKIN Period 20 100 22.5 100 25 100 30 100 ns
t
CKL
CLKIN Width Low 7777ns
t
CKH
CLKIN Width High 5555ns
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 ns
Figure 9. Clock Input
CLKIN
t
CKH
t
CKL
t
CK
Table 8. Reset
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
WRST
RESET Pulse Width Low
1
4t
CK
ns
t
SRST
RESET Setup Before CLKIN High
2
14 + DT/2 t
CK
ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
V
DD
and CLKIN (not including startup time of external clock oscillator).
2
Only required if multiple ADSP-21061s must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21061s commu-
nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
Figure 10. Reset
CLKIN
RESET
t
WRST
t
SRST