Datasheet

Rev. F | Page 6 of 64 | March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Figure 3. Shared Memory Multiprocessing System
ADDR31–0
CPA
BMS
C
O
N
T
R
O
L
ADSP-2106x #1
5
CONTROL
ADSP-2106x #2
ADDR31–0
CONTROL
ADSP-2106x #3
5
ID2–0
RESET
RPBA
CLKIN
ID2–0
RESET
RPBA
ID2–0
RESET
RPBA
CLKIN
ADSP-2106x #6
ADSP-2106x #5
ADSP-2106x #4
CLOCK
RESET
ADDR
DATA
HOST PROCESSOR
INTERFACE (OPTIONAL)
ACK
GLOBAL MEMORY
AND
PERIPHERAL (OPTIONAL)
OE
ADDR
DATA
CS
ADDR
DATA
BOOT EPROM (OPTIONAL)
RDx
MS3–0
SBTS
CS
ACK
ADDR31–0
CLKIN
3
001
PAGE
3
010
3
011
BR1
BR2–6
REDY
HBG
HBR
CS
WE
WRx
5
C
O
N
T
R
O
L
A
D
D
R
E
S
S
D
A
T
A
C
O
N
T
R
O
L
A
D
D
R
E
S
S
D
A
T
A
DATA47–0
BR1–2, BR4–6
BR3
DATA47–0
BR1, BR3–6
BR2
DATA47–0
BUS
PRIORITY
CPA