Datasheet

Rev. F | Page 40 of 64 | March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Table 27. Link Ports—Transmit
5 V 3.3 V
Unit
Parameter Min Max Min Max
Timing Requirements
t
SLACH
LACK Setup Before LCLK High 19 19 ns
t
HLACH
LACK Hold After LCLK High –6.75 –6.5 ns
Switching Characteristics
t
DLCLK
Data Delay After CLKIN 8 8 ns
t
DLDCH
Data Delay After LCLK High
1
2.25 2.25 ns
t
HLDCH
Data Hold After LCLK High
2
–2.0 –2 ns
t
LCLKTWL
LCLK Width Low
3
(t
CK
/4) – 1 (t
CK
/4) + 1.25 (t
CK
/4) – 0.75 (t
CK
/4) + 1.5 ns
t
LCLKTWH
LCLK Width High
4
(t
CK
/4) – 1.25 (t
CK
/4) + 1 (t
CK
/4) – 1.5 (t
CK
/4) + 1 ns
t
DLACLK
LCLK Low Delay After LACK High (t
CK
/4) + 9 (3 u t
CK
/4) + 16.5 (t
CK
/4) + 9 (3 u t
CK
/4) + 16.5 ns
1
For ADSP-21060/ADSP-21060C, specification is 2.5 ns max.
2
For ADSP-21062L, specification is –2.25 ns min.
3
For ADSP-21060, specification is (t
CK
/4) – 1ns min, (t
CK
/4) + 1 ns max; for ADSP-21060C/ADSP-21062L, specification is (t
CK
/4) – 1 ns min, (t
CK
/4) + 1.5 ns max.
4
For ADSP-21060, specification is (t
CK
/4) – 1 ns min, (t
CK
/4) + 1 ns max; for ADSP-21060C, specification is (t
CK
/4) – 1.5 ns min, (t
CK
/4) + 1 ns max.