Datasheet

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F | Page 37 of 64 | March 2008
Figure 23. DMA Handshake
CLKIN
t
SDRLC
DMARx
DATA
(OUT)
DATA
(IN)
RD
WR
t
WDR
t
SDRHC
t
DMARH
t
DMARLL
t
HDGC
t
WDGH
t
DDGL
DMAG x
t
VDATDGH
t
DATDRH
t
DATRDGH
t
HDATIDG
t
DGWRL
t
DGWRH
t
DGWRR
t
DGRDL
t
DRDGH
t
DGRDR
t
SDATDGL
*MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER
TIMING SPECIFICATIONS FOR ADDR31–0, RD, WR, SW MS3–0, AND ACK ALSO APPLY HERE.
(EXTERNAL DEVICE TO EXTERNAL MEMORY)
(EXTERNAL MEMORY TO EXTERNAL DEVICE)
TRANSFERS BETWEEN ADSP-2106x
INTERNAL MEMORY AND EXTERNAL DEVICE
TRANSFERS BETWEEN EXTERNAL DEVICE AND
EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
t
DDGHA
ADDR
MSx, SW
t
DADGH
t
WDGL
(FROM EXTERNAL DEVICE TO ADSP-2106x)
(FROM ADSP-2106x TO EXTERNAL DEVICE)