Datasheet

Rev. F | Page 24 of 64 | March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Flags
Table 13. Flags
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SFI
FLAG3–0 IN Setup Before CLKIN High
1
8 + 5DT/16 ns
t
HFI
FLAG3–0 IN Hold After CLKIN High
1
0 – 5DT/16 ns
t
DWRFI
FLAG3–0 IN Delay After RD/WR Low
1
5 + 7DT/16 ns
t
HFIWR
FLAG3–0 IN Hold After RD/WR Deasserted
1
0ns
Switching Characteristics
t
DFO
FLAG3–0 OUT Delay After CLKIN High 16 ns
t
HFO
FLAG3–0 OUT Hold After CLKIN High 4 ns
t
DFOE
CLKIN High to FLAG3–0 OUT Enable 3 ns
t
DFOD
CLKIN High to FLAG3–0 OUT Disable 14 ns
1
Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.
Figure 13. Flags
CLKIN
FLAG3–0 OUT
FLAG OUTPUT
CLKIN
FLAG INPUT
t
DFO
t
HFO
t
DFO
t
DFOD
t
DFOE
t
SFI
t
HFI
t
HFIWR
t
DWRFI
RD/WR
FLAG3–0 IN