Datasheet

Rev. F | Page 18 of 64 | March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
ADSP-21060L/ADSP-21062L SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS (3.3 V)
ELECTRICAL CHARACTERISTICS (3.3 V)
A Grade C Grade K Grade
Parameter Description Min Max Min Max Min Max Unit
V
DD
Supply Voltage 3.15 3.45 3.15 3.45 3.15 3.45 V
T
CASE
Case Operating Temperature –40 +85 –40 +100 –40 +85 qC
V
IH
1
1
1
Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA,
TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1
High Level Input Voltage @ V
DD
= Max 2.0 V
DD
+ 0.5 2.0 V
DD
+ 0.5 2.0 V
DD
+ 0.5 V
V
IH
2
2
2
Applies to input pins: CLKIN, RESET, TRST
High Level Input Voltage @ V
DD
= Max 2.2 V
DD
+ 0.5 2.2 V
DD
+ 0.5 2.2 V
DD
+ 0.5 V
V
IL
1, 2
Low Level Input Voltage @ V
DD
= Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V
Parameter Description Test Conditions Min Max Unit
V
OH
1, 2
High Level Output Voltage @ V
DD
= Min, I
OH
= –2.0 mA 2.4 V
V
OL
1, 2
Low Level Output Voltage @ V
DD
= Min, I
OL
= 4.0 mA 0.4 V
I
IH
3, 4
High Level Input Current @ V
DD
= Max, V
IN
= V
DD
Max 10 μA
I
IL
3
Low Level Input Current @ V
DD
= Max, V
IN
= 0 V 10 μA
I
ILP
4
Low Level Input Current @ V
DD
= Max, V
IN
= 0 V 150 μA
I
OZH
5, 6, 7, 8
Three-State Leakage Current @ V
DD
= Max, V
IN
= V
DD
Max 10 μA
I
OZL
5, 9
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 10 μA
I
OZHP
9
Three-State Leakage Current @ V
DD
= Max, V
IN
= V
DD
Max 350 μA
I
OZLC
7
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 1.5 mA
I
OZLA
10
Three-State Leakage Current @ V
DD
= Max, V
IN
= 1.5 V 350 μA
I
OZLAR
8
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 4.2 mA
I
OZLS
6
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 150 μA
C
IN
11, 12
Input Capacitance f
IN
= 1 MHz, T
CASE
= 25°C, V
IN
= 2.5 V 4.7 pF
1
Applies to output and bidirectional pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2,
BR6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.
2
See “Output Drive Currents” for typical drive current capabilities.
3
Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
4
Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.
5
Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx,
TDO, EMU
. (Note that ACK is pulled up internally with 2 k: during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus
mastership.)
6
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
7
Applies to CPA pin.
8
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k: during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL
is not requesting bus mastership).
9
Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK.
10
Applies to ACK pin when keeper latch enabled.
11
Applies to all signal pins.
12
Guaranteed but not tested.