Datasheet

ADPD1080/ADPD1081 Data Sheet
Rev. B | Page 66 of 74
Address Data Bit
Default
Value Access Name Description
0x59 15 0x0 R/W Reserved Write 0x0.
[14:13] 0x0 R/W FLT_EN_B 0: default setting, float disabled for Time Slot B.
1: reserved.
2: reserved.
3: enable float mode.
[12:8] 0x08 R/W FLT_PRECON_B Float mode preconditioning time for Time Slot B. Time to start of
first float time, which is typically 16 µs.
[7:0] 0x08 R/W Reserved Write 0x08.
0x5A [15:12] 0x0 R/W FLT_LED_FIRE_B In any given sequence of four pulses, fire the LED in the selected
position by writing a zero into that pulse position. Mask the LED
pulse (that is, do not fire LED) by writing a 1 into that position. In a
sequence of four pulses on Time Slot B, Register 0x5A, Bit 12, is
the first pulse, Bit 13 is the second pulse, Bit 14 is the third pulse,
and Bit 15 is the fourth pulse.
[11:8] 0x0 R/W FLT_LED_FIRE_A In any given sequence of four pulses, fire the LED in the selected
position by writing a zero into that pulse position. Mask the LED
pulse (that is, do not fire LED) by writing a 1 into that position. In a
sequence of four pulses on Time Slot A, Register 0x5A, Bit 8, is the
first pulse, Bit 9 is the second pulse, Bit 10 is the third pulse, and
Bit 11 is the fourth pulse.
[7:0] 0x10 R/W Reserved Write 0x10.
0x5E 15 0x0 R/W Reserved Write 0x0.
[14:13] 0x0 R/W FLT_EN_A 0: default setting, float disabled for Time Slot A.
1: reserved
2: reserved
3: enable float mode in Time Slot A.
[12:8] 0x08 R/W FLT_PRECON_A Float mode preconditioning time for Time Slot A. Time to start of
first float time, which is typically 16 µs.
[7:0] 0x08 R/W Reserved Write 0x08.
SYSTEM REGISTERS
Table 42. System Registers
Address Data Bit
Default
Value Access Name Description
0x00 [15:8] 0x00 R/W FIFO_SAMPLES FIFO status. Number of available bytes to be read from the FIFO.
When comparing this to the FIFO length threshold (Register 0x06,
Bits[13:8]), note that the FIFO status value is in bytes and the FIFO
length threshold is in words, where one word = two bytes.
Write 1 to Bit 15 to clear the contents of the FIFO.
7 0x0 R/W Reserved Write 0x1 to clear this bit to 0x0.
6 0x0 R/W SLOTB_INT Time Slot B interrupt. Describes the type of interrupt event. A 1
indicates an interrupt of a particular event type has occurred. Write a
1 to clear the corresponding interrupt. After clearing, the register
goes to 0. Writing a 0 to this register has no effect.
5 0x0 R/W SLOTA_INT Time Slot A interrupt. Describes the type of interrupt event. A 1
indicates an interrupt of a particular event type has occurred. Write a
1 to clear the corresponding interrupt. After clearing, the register
goes to 0. Writing a 0 to this register has no effect.
[4:0] 0x00 R/W Reserved Write 0x1F to clear these bits to 0x00.
0x01 [15:9] 0x00 R/W Reserved Write 0x00.
8 0x1 R/W FIFO_INT_MASK Sends an interrupt when the FIFO data length has exceeded the
FIFO length threshold in Register 0x06, Bits[13:8]. A 0 enables the
interrupt.
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