Datasheet

ADPD1080/ADPD1081 Data Sheet
Rev. B | Page 62 of 74
Address Data Bit
Default
Value Access Name Description
[3:2] 0x0 R/W SLOTA_TIA_GAIN_3 TIA gain for Time Slot A, Channel 3 when Register 0x42,
Bit 6 = 1.
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
[1:0] 0x0 R/W SLOTA_TIA_GAIN_2 TIA gain for Time Slot A, Channel 2 when Register 0x42,
Bit 6 = 1.
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
Table 39. AFE Configuration Registers, Time Slot A
Address Data Bit
Default
Value Access Name Description
0x17 [15:4] 0x000 R/W Reserved Write 0x000
[3:0] 0x0 R/W INTEG_ORDER_A Integration sequence order for Time Slot A. Each bit
corresponds to the polarity of the integration sequence of a
single pulse in a four-pulse sequence. Bit 0 controls the
integration sequence of Pulse 1, Bit 1 controls Pulse 2, Bit 2
controls Pulse 3, and Bit 3 controls Pulse 4. After four pulses,
the sequence repeats.
0: normal integration sequence.
1: reversed integration sequence.
0x39 [15:11] 0x4 R/W SLOTA_AFE_WIDTH AFE integration window width (in 1 µs step) for Time Slot A.
[10:0] 0x2FC R/W SLOTA_AFE_OFFSET AFE integration window offset for Time Slot A in 31.25 ns steps.
0x42 [15:10] 0x07 R/W SLOTA_AFE_MODE Set to 0x07.
[9:8] 0x0 R/W SLOTA_INT_GAIN For normal mode,
00: R
INT
= 400 kΩ.
01: R
INT
= 200 kΩ.
10: R
INT
= 100 kΩ.
For TIA ADC mode with integrator configured as buffer,
00: integrator as buffer gain = 1.0.
01: integrator as buffer gain = 1.0.
10: integrator as buffer gain = 0.7.
7 0x0 R/W SLOTA_INT_AS_BUF 0: normal integrator configuration.
1: converts integrator to buffer amplifier (used in TIA ADC
mode only).
6 0x0 R/W SLOTA_TIA_IND_EN Enable Time Slot A TIA gain individual settings. When it is
enabled, the Channel 1 TIA gain is set via Register 0x42,
Bits[1:0], and the Channel 2 through Channel 4 TIA gain is
set via Register 0x55, Bits[5:0].
0: disable TIA gain individual setting.
1: enable TIA gain individual setting.
[5:4] 0x3 R/W SLOTA_TIA_VREF Set V
REF
of the TIA for Time Slot A.
0: 1.14 V.
1: 1.01 V.
2: 0.90 V.
3: 1.27 V (default recommended).
[3:2] 0x2 R/W Reserved Reserved. Write 0x1.
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