Datasheet

Data Sheet ADPD1080/ADPD1081
Rev. B | Page 51 of 74
Table 32. Float LED Mode Registers
Register Address
Group Register Name Time Slot A Time Slot B Float Mode Description
Float Mode
Operation
SLOTx_LED_SEL 0x14, Bits[1:0] 0x14, Bits[3:2] Set to 0 to enable float mode.
FLT_EN1_x 0x5E, Bits[14:13] 0x59, Bits[14:13] Set to 3 to enable float between connect pulses.
FLT_MATH12_x 0x58, Bits[2:1] 0x58, Bits[6:5] Set to 2 to subtract first pulse and add second pulse.
FLT_MATH34_x 0x58, Bits[9:8] 0x58, Bits[11:10] Set to 1 to add third pulse and subtract fourth pulse.
SLOTx_AFE_CFG 0x43, Bits[15:0] 0x45, Bits[15:0] Set to 0xAE65 for TIA + integrator, bypass BPF.
SLOTx_TIA_VREF 0x42, Bits[5:4] 0x44, Bits[5:4] Set to 2 for TIA_VREF = 0.9 V.
SLOTx_V_CATHODE 0x54, Bits[9:8] 0x54, Bits[11:10] Set to 2 for 250 mV reverse bias on the photodiode at the
precondition.
REG54_VCAT_ENABLE 0x54, Bit 7 0x54, Bit 7 Set to 1 to override Register 0x3C cathode voltage settings.
FLT_LED_SELECT_x 0x3E, Bits[15:14] 0x3F[15:14] LED selection for float LED mode.
00 = no LED.
01 = LED1.
10 = LED2.
11 = LED3.
Float Mode
Timing
FLT_PRECON_x 0x5E, Bits[12:8] 0x59, Bits[12:8] Precondition time (to start of float 1 time).
SLOTx_PERIOD 0x31, Bits[7:0] 0x36, Bits[7:0] 8 LSBs of float period in µs. Float 2 time = SLOTx_PERIOD.
Float 2 time is valid for every pulse subsequent to the first
pulse. Float 1 time must be set equal to Float 2 time in
float LED mode.
SLOTx_PERIOD 0x37, Bits[1:0] 0x37, Bits[9:8] 2 MSBs of float period.
SLOTx_LED_WIDTH 0x30, Bits[12:8] 0x35, Bits[12:8] Connect time in µs, which is the amount of time given to
dump the accumulated charge from the photodiode
capacitance. Typically, it is set to 2 µs.
SLOTx_LED_OFFSET 0x30, Bits[7:0] 0x35, Bits[7:0] Time to first charge dump. Float 1 time =
(SLOTx_LED_OFFSET + SLOTx_LED_WIDTH) –
FLT_PRECONx. Float 1 time must be equal to Float 2 time
for float LED mode.
SLOTx_AFE_WIDTH 0x39,Bits[15:11] 0x3B, Bits[15:11] Integration time in µs. set to FLT_CONN + 1.
SLOTx_AFE_OFFSET 0x39, Bits[10:0] 0x3B, Bits[10:0] Integrator start time in 31.25 ns increments. Set to
(SLOTx_LED_OFFSET – SLOTx_AFE_WIDTH − 9.25) µs.
SLOTx_PULSES 0x31, Bits[15:8] 0x36, Bits[15:8] Number of pulses; must be set in multiples of 2,
minimum 2.
FLT_LED_WIDTH_x 0x3E, Bits[12:8] 0x3F, Bits[12:8] LED pulse width for float LED mode in µs.
FLT_LED_OFFSET_x 0x3E, Bits[7:0] 0x3F, Bits[7:0] Time of first LED pulse in float LED mode.
FLT_LED_FIRE_x 0x5A, Bits[11:8] 0x5A, Bits[15:12] In any given sequence of four pulses, fire the LED in the
selected position. Selections are active low (that is, fire LED
if 0). For example, in a sequence of four pulses on Time Slot B,
Register 0x5A, Bit 12 is the first pulse, and Register 0x5A,
Bit 15 is the fourth pulse. For a sequence of four pulses, fire
the LED in the second and third pulses by writing 0x9 to
Register 0x5A, Bits[15:12].
A timing diagram for a four pulse float LED sequence for
Time Slot B is shown in Figure 55. In this example, the device is
set up for LED pulses of 12 µs that fall within a float period of
16 µs, 2 µs of which are used for dumping of the accumulated
charge on the photodiode. The integration time is set to 3 µs,
which is 1 µs more than the charge dump time to allow timing
margin when integrating the incoming charge. Note, there is a
9 µs offset built into the integration start time. Consider this
offset when setting the SLOTx_AFE_OFFSET value. As shown
in Figure 55, the time of the first charge dump is set to 30 µs.
SLOTx_AFE_OFFSET is set to 0x238 (17.75 µs), taking into
account the 3 µs integration time, the 9 µs offset, and an
additional 250 ns for edge placement margin.
To calculate SLOTx_AFE_OFFSET, use the following equation:
SLOTx_AFE_OFFSET = SLOTx_LED_OFFSET –
SLOTx_AFE_WIDTH − 9.25 µs
Placement of the integration period is such that the negative
phase of the integration is centered on the charge dump phase.
The TIA is an inverting stage; therefore, placing the negative
phase of the integration during the dumping of the charge from
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