Datasheet

ADPD1080/ADPD1081 Data Sheet
Rev. B | Page 48 of 74
CONNECT/FLOAT
25µs 30µs 35µs
INTEGRATOR
DON’T CARE
+PHASE –PHASE
CHARGE ON PD
TIA OUTPUT
INTEGRATOR RESPONSE
INTEGRATOR RESET
ADC READ
A D E
B C F
16110-050
Figure 52. Float Mode Measurement Cycle Timing Diagram
Float Mode Limitations
When using float mode, the limitations of the mode must be
well understood. For example, a finite amount of charge can
accumulate on the capacitance of the photodiode, and a maximum
amount of charge that can be integrated by the integrator.
Based on an initial reverse bias of 250 mV on the photodiode
and assuming that the photodiode begins to become nonlinear
at ~200 mV of forward bias, there is ~450 mV of headroom for the
anode voltage to increase from its starting point at the beginning
of the float time before the charge ceases to accumulate in a
linear fashion. It is desirable to operate only in the linear region
of the photodiode (see Figure 53). To verify that float mode is
operating in the linear region of the diode, the user can perform
a simple check. Record data at a desired float time and then
record data at half the float time. The ratio of the two received
signals should be 2:1. If this ratio does not hold true, the diode
is likely beginning to forward bias at the longer float time and
becomes nonlinear.
INTEGRATED CHARGE ON PD (pC)
FLOAT TIME (µs)
RECOMMENDED
FLOAT MODE
OPERATING REGION
PD BEGINS TO
FORWARD BIAS
16110-051
Figure 53. Transfer Function of Integrated Charge on the Photodiode vs.
Float Time
The maximum amount of charge that can be stored on the
photodiode capacitance and remain in the linear operating
region of the sensor can be estimated by
Q = CV
where:
Q is the integrated charge.
C is the capacitance of the photodiode.
V is the amount of voltage change across the photodiode before
the photodiode becomes nonlinear.
For a typical discrete optical design using a 7 mm
2
photodiode
with 70 pF capacitance and 450 mV of headroom, the maximum
amount of charge that can be stored on the photodiode
capacitance is 31.5 pC.
In addition, consider the maximum amount of charge the
integrator of the ADPD1080/ADPD1081 can integrate. The
integrator can integrate up to 7.6 pC. When this charge is referred
back to the input, consider the TIA gain. When the TIA gain is
at 200 kΩ, the input referred charge is at a 1:1 ratio to the
integrated charge on the integrator. For 100 kΩ gain, it is 2:1;
for 50 kΩ gain, it is 4:1; and for 25 kΩ gain, it is 8:1. For the
previous example using a photodiode with 70 pF capacitance,
use 50 kΩ TIA gain and set the float timing such that, for a single
pulse, the output of the ADC is at 70% of full scale, which is a
typical operating condition. Under these operating conditions,
5.3 pC integrates per pulse by the integrator for 21.2 pC of charge
accumulated on the photodiode capacitance. For small CTR,
however, it can take a long time to accumulate 21.2 pC of charge
on the photodiode capacitance, in which case, use higher TIA
gains according to how much charge can be accumulated in a
given amount of time. Ultimately, the type of measurement
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