Datasheet

Data Sheet ADPD1080/ADPD1081
Rev. B | Page 43 of 74
TIA ADC MODE
Figure 49 shows a way to put the devices into a mode that
effectively runs the TIA directly into the ADC without using
the analog BPF and integrator. This mode is referred to as TIA
ADC mode. There are two basic applications of TIA ADC mode.
In normal operation, all background light is blocked from the
signal chain and, therefore, cannot be measured. TIA ADC
mode can measure the amount of background and ambient light.
This mode can also measure other dc input currents, such as
leakage resistance.
TIA_VREF
16110-047
OPTIONAL
BUFFER
–1
TIA
ADC
Figure 49. TIA ADC Mode Block Diagram
When the devices are in TIA ADC mode, the BPF and the
integrator stage are bypassed. This bypass effectively wires the
TIA directly into the ADC. At the set sampling frequency, the
ADC samples Channel 1 through Channel 4 in sequential order,
and each sample is taken at 1 µs intervals.
There are two modes of operation in TIA ADC mode. One
mode is an inverting configuration where TIA ADC mode
directly drives the ADC. This mode is enabled by setting
Register 0x43 (Time Slot A) and/or Register 0x45 (Time Slot B)
to 0xB065, which bypasses the BPF and the integrator. With the
ADC offset register(s) for the desired channel set to 0, and the
bias voltage for the TIA (TIA_VREF) set to 1.265 V, the output
of the ADC is at ~13,000 codes for a single pulse and a zero
input current condition. As the input current from the
photodiode increases, the ADC output decreases toward 0.
This configuration is a legacy TIA ADC mode from the
ADPD103 that is kept in the ADPD1080/ADPD1081 for
backward compatibility.
The recommended TIA ADC mode is one in which the BPF is
bypassed and the integrator is configured as an inverting buffer.
This mode is enabled by writing 0xAE65 to Register 0x43
(Time Slot A) and/or Register 0x45 (Time Slot B) to bypass
the BPF. Additionally, to configure the integrator as a buffer,
set Bit 7 of Register 0x42 (Time Slot A) and/or Register 0x44
(Time Slot B) to 1, and set Bit 7 of Register 0x58 to 1. With
the ADC offset register(s) for the desired channel set to 0
and the TIA_VREF set to 1.265 V, the output of the ADC is
at ~13,000 codes for a single pulse and a zero input current
condition. As the input current from the photodiode increases,
the ADC output decreases toward 0.
When configuring the integrator as a buffer, there is the option
of either using a gain of 1 or a gain of 0.7. Using the gain of 0.7
increases the usable dynamic range at the input to the TIA;
however, it is possible to overrange the ADC in this configuration
and care must be taken to not saturate the ADC. To set the buffer
gain use Register 0x42, Bit 9 for Time Slot A and Register 0x44,
Bit 9 for Time Slot B. Setting this bit to 0 (default) sets a gain of
1. Setting this bit to 1 configures the buffer with a gain of 0.7.
Calculate the ADC output (ADC
OUT
) as follows:
ADC
OUT
= 8192 ± (((2 × TIA_VREF − 2 × i × R
F
− 1.8 V)/
146 µV/LSB) × SLOTx_BUF_GAIN) (11)
where:
TIA_VREF is the bias voltage for the TIA (the default value is
1.265 V).
i is the input current to the TIA.
R
F
is the TIA feedback resistor.
SLOTx_BUF_GAIN is either 0.7 or 1 based on the setting of
Register 0x42, Bit 9 and Register 0x44, Bit 9.
Equation 11 is an approximation and does not account for
internal offsets and gain errors. The calculation also assumes
that the ADC offset registers are set to 0
One time slot can be used in TIA ADC mode at the same time
the other time slot is being used in normal pulsed mode. This
capability is useful for monitoring ambient and pulsed signals at
the same time. The ambient signal is monitored during the time
slot configured for TIA ADC mode, while the pulsed signal,
with the ambient signal rejected, is monitored in the time slot
configured for normal mode.
Protecting Against TIA Saturation in Normal Operation
One of the reasons to monitor TIA ADC mode is to protect
against environments that may cause saturation. One concern
when operating in high light conditions, especially with larger
photodiodes, is that the TIA stage may become saturated while
the ADPD1080/ADPD1081 continue to communicate data. The
resulting saturation is not typical. The TIA, based on its settings,
can only handle a certain level of photodiode current. Based on
the way the ADPD1080/ADPD1081 are configured, if there is a
current level from the photodiode that is larger than the TIA can
handle, the TIA output during the LED pulse effectively extends
the current pulse, making it wider. The AFE timing is then violated
because the positive portion of the BPF output extends into the
negative section of the integration window. Thus, the photo signal
is subtracted from itself, causing the output signal to decrease
when the effective light signal increases.
To measure the response from the TIA and verify that this stage
is not saturating, place the device in TIA ADC mode and slightly
modify the timing. Specifically, sweep SLOTx_AFE_OFFSET
until two or three of the four channels reach a minimum value
(note that TIA is in an inverting configuration). The four channels
do not reach this minimum value because, typically, 3 µs LED
pulse widths are used, and the ADC samples the four channels
sequentially at 1 µs intervals. This procedure aligns the ADC
sampling time with the LED pulse to measure the total amount of
light falling on the photodetector (for example, background light +
LED pulse).
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