Datasheet
Data Sheet ADPD1080/ADPD1081
Rev. B | Page 37 of 74
Table 24. ADPD1080/ADPD1081 Settings Used for Timing Diagrams Shown in Figure 43 and Figure 44
Register Setting Description
0x31 0x0118 Time Slot A: 1 LED pulse
0x36 0x0418 Time Slot B: 4 LED pulses
0x15 0x0120 Time Slot A decimation = 4, Time Slot B decimation = 2
SLOT A
SLOT B
SLOT B
SLOT A
SLEEP
16110-043
Figure 43. Optional Timing Signals Available on GPIOx—Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x05, 0x06, 0x07, and 0x0F
SLOT A/B SLOT A/B SLOT A/B SLOT A/B SLOT A/B SLOT A/B
0x02
0x0D
0x0E
0x0C
SLEEP
SLEEP
SLEEP SLEEP
SLEEP
16110-044
Figure 44. Optional Timing Signals Available on GPIOx—Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x0C, 0x0D, and 0x0E
ADPD103 Backward Compatibility
Setting Register 0x0B = 0 provides backward compatibility to
the ADPD103. The GPIO0 pin mirrors the functionality of the
ADPD103 INT pin. The GPIO1 pin mirrors the functionality of
the ADPD103 PDSO pin.
Interrupt Function
Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x01 configures
the respective pin to perform the interrupt function as defined
by the settings in Register 0x01.
Sample Timing
Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02 configures
the respective pin to provide a signal that asserts at the beginning
of the first time slot of the current sample and deasserts at the
end of the last time slot of the current sample. For example, if
both time slots are enabled, this signal asserts at the beginning
of Time Slot A and deasserts at the end of Time Slot B. If only a
single time slot is enabled, the signal asserts at the beginning of
the enabled time slot and deasserts at the end of this same time slot.
Pulse Outputs
Three options are available to provide a copy of the LED pulse
outputs. Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x05
provides a copy of the Time Slot A LED pulses on the respective
pin. A setting of 0x06 provides the Time Slot B pulses, and a
setting of 0x07 provides the pulse outputs of both time slots.
Output Data Cycle Signal
Three options are available to provide a signal that indicates
when the output data is written to the output data registers or to
the FIFO. Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x0C
provides a signal that indicates that a data value is written for
Time Slot A. A setting of 0x0D provides a signal that indicates
that a data value is written for Time Slot B, and a setting of 0x0E
provides a signal to indicate that a value is written for either
time slot. The signal asserts at the end of the time slot, when the
output data is already written, and deasserts at the start of the
subsequent sample. This timing signal is especially useful in
situations where the FIFO is used. For example, one of the GPIOx
pins can provide an interrupt after the FIFO reaches the FIFO
threshold set in Register 0x06, Bits[13:8], while the other
GPIOx pin can provide the output data cycle signal. This signal
can trigger a peripheral device, such as an accelerometer, so that
time aligned signals are provided to the processor.
f
S
/2 Output
Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x0F configures
the respective pin to provide a signal that toggles at half the
sampling rate. This timing signal is useful in, for example,
situations where more than two LEDs per sample are required.
This signal can be used as a select signal to a multiplexer being
used to mux two LEDs into a single LED driver, providing the
ability to drive up to four separate LEDs per sample period.
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