Datasheet

ADPD1080/ADPD1081 Data Sheet
Rev. B | Page 36 of 74
Because a new sample may arrive while the reads are occurring,
this method prevents the new sample from partially overwriting
the data being read.
CLOCKS AND TIMING CALIBRATION
The ADPD1080/ADPD1081 operate using two internal time
bases: a 32 kHz clock sets the sample timing, and a 32 MHz
clock controls the timing of the internal functions, such as
LED pulsing and data capture. Both clocks are internally
generated and exhibit device to device variation of
approximately 10% (typical).
Heart rate monitoring applications require an accurate time
base to achieve an accurate count of beats per minute. The
ADPD1080/ADPD1081 provide a simple calibration procedure
for both clocks.
Calibrating the 32 kHz Clock
Calibrating the 32 kHz clock also calibrates items associated
with the output data rate. Calibration of this clock is important
for applications where an accurate data rate is important, such
as heart rate measurements.
To calibrate the 32 kHz clock,
1. Set the sampling frequency to the highest the system can
handle, such as 2000 Hz. Because the 32 kHz clock controls
sample timing, its frequency is readily accessible via the
GPIO0 pin. Configure the interrupt by writing the appropriate
value to the bits in Register 0x02 and set the interrupt to occur
at the sampling frequency by writing 0 to Register 0x01,
Bit 5 or Bit 6. Monitor the GPIO0 pin. The interrupt
frequency must match the set sample frequency.
2. If the monitored interrupt frequency is less than the set
sampling frequency, decrease the CLK32K_ADJUST bit
(Register 0x4B, Bits[5:0]). If the monitored interrupt
frequency is larger than the set sampling frequency,
increase the CLK32K_ADJUST bits.
3. Repeat Step 1 and Step 2 until the monitored interrupt
signal frequency is close enough to the set sampling
frequency.
After the 32 kHz oscillator calibration completes, set the GPIO0
pin to the mode desired for normal operation.
Calibrating the 32 MHz Clock
Calibrating the 32 MHz clock also calibrates items associated with
the fine timing within a sample period, such as LED pulse width
and spacing, assuming that the 32 kHz clock is calibrated.
To calibrate the 32 MHz clock, the 32 kHz clock must first be
calibrated as previously described. Always start this routine with
Register 0x4D set to 0x98, which is the default value at power-up.
1. Write 0x1 to Register 0x5F, Bit 0 (DIGITAL_CLOCK_ENA)
to enable the 32 MHz oscillator.
2. Enable the CLK_RATIO calculation by writing 0x1 to
Register 0x50, Bit 5 (CLK32M_CAL_EN). This function
counts the number of 32 MHz clock cycles in two cycles of
the 32 kHz clock. With this function enabled, this cycle
value is stored in Register 0x0A, Bits[11:0] and nominally
this ratio is 2000 (0x7D0).
3. Calculate the 32 MHz clock error as follows:
Clock Error = 32 MHz × (1 − CLK_RATIO/2000)
4. Adjust the frequency of the 32 MHz oscillator by adjusting
the setting of Bits[7:0] in Register 0x4D by the amount
calculated in the following equation:
CLK32M_ADJUST = Clock Error/112 kHz
5. Write 0x0 to Register 0x50, Bit 5 (CLK32M_CAL_EN) to
reset the CLK_RATIO function.
Repeat Step 2 through Step 5 until the desired accuracy is achieved.
Write 0x0 to Register 0x5F, Bit 0 to disable the 32 MHz oscillator.
OPTIONAL TIMING SIGNALS AVAILABLE ON
GPIO0 AND GPIO1
The ADPD1080/ADPD1081 provide a number of different
timing signals, available via the GPIO0 and GPIO1 pins, to enable
ease of system synchronization and flexible triggering options.
Each GPIOx pin can be configured as an open-drain output if
the pins are to share the bus with other drivers, or the pins can
be configured to always drive the bus. Both outputs also have
polarity control in situations where a timing signal must be
inverted from the default.
Table 23. GPIOx Control Settings
Mnemonic Register, Bit Setting Description
GPIO0 0x02, Bit 0 0: polarity active high
1: polarity active low
0x02, Bit 1 0: always drives the bus
1: drives the bus when asserted
0x02, Bit 2 0: disables the GPIO0 pin drive
1: enables the GPIO0 pin drive
GPIO1 0x02, Bit 8 0: polarity active high
1: polarity active low
0x02, Bit 9 0: always drives the bus
1: drives the bus when asserted
0x4F, Bit 6 0: disables the GPIO1 pin drive
1: enables the GPIO1 pin drive
The various available timing signals are controlled by the settings in
Register 0x0B. Bits[12:8] of this register control the timing signals
available on GPIO1, and Bits[4:0] control the timing signals
available on GPIO0. All of the timing signals described in this data
sheet are available on either (or both) of the GPIO0 and GPIO1
pins. Timing diagrams are shown in Figure 43 and Figure 44.
The time slot settings used to generate the timing diagrams are
described in Table 24.
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