Datasheet

ADPD1080/ADPD1081 Data Sheet
Rev. B | Page 34 of 74
derating of the capacitor value over voltage, bias, temperature,
and other factors over the life of the component.
LED INDUCTANCE CONSIDERATIONS
The LED drivers (LEDXx) on the ADPD1080/ADPD1081
have configurable slew rate settings (Register 0x22, Bits[6:4],
Register 0x23, Bits[6:4], and Register 0x24, Bits[6:4]). These
slew rates are defined in Table 3. Even at the lowest setting,
carefully consider board design and layout. If a large series
inductor, such as a long PCB trace, is placed between the LED
cathode and one of the LEDXx pins, voltage spikes from the
switched inductor can cause violations of absolute maximum
and minimum voltages on the LEDXx pins during the slew
portion of the LED pulse.
To verify that there are no voltage spikes on the LEDXx pins due
to parasitic inductance, use an oscilloscope on the LEDXx pins to
monitor the voltage during normal operation. Any positive spike
>3.6 V may damage the devices.
In addition, a negative spike less than −0.3 V may also damage the
devices.
RECOMMENDED START-UP SEQUENCE
At power-up, the device is in standby mode (Register 0x10 =
0x0000), as shown in Figure 27. The ADPD1080/ADPD1081 do
not require a particular power-up sequence.
From standby mode, to begin measurement, initiate the
ADPD1080/ADPD1081 as follows:
1. Set the CLK32K_EN bit (Register 0x4B, Bit 7) to start the
sample clock (32 kHz clock). This clock controls the state
machine. If this clock is off, the state machine is not able to
transition as defined by Register 0x10.
2. Write 0x1 to Register 0x10 to force the device into program
mode. Step 1 and Step 2 can be swapped, but the actual
state transition does not occur until both steps occur.
3. Write additional control registers in any order while the
device is in program mode to configure the devices as
required.
4. Write 0x2 to Register 0x10 to start normal sampling
operation.
To terminate normal operation, follow this sequence to place
the ADPD1080/ADPD1081 in standby mode:
1. Write 0x1 to Register 0x10 to force the devices into
program mode.
2. Write to the registers in any order while the devices are in
program mode.
3. Write 0x00FF to Register 0x00 to clear all interrupts. If
desired, clear the FIFO as well by writing 0x80FF to
Register 0x00.
4. Write 0x0 to Register 0x10 to force the devices into standby
mode.
Optionally, stop the 32 kHz clock by resetting the CLK32K_
EN bit (Register 0x4B, Bit 7). Register 0x4B, Bit 7 = 0 is the
only write that must be written when the device is in standby
mode (Register 0x10 = 0x0). If 0 is written to this bit while in
program mode or normal mode, the devices become
unable to transition into any other mode, including standby
mode, even if they are subsequently written to do so. As a
result, the power consumption in what appears to be standby
mode is greatly elevated. For this reason, and due to the low
current draw of the 32 kHz clock while in operation, it is
recommended from an ease of use perspective to keep the
32 kHz clock running after it is turned on.
READING DATA
The ADPD1080/ADPD1081 provide multiple methods for
accessing the sample data. Each time slot can be independently
configured to provide data access using the FIFO or the data
registers. Interrupt signaling is also available to simplify timely
data access. The FIFO is available to loosen the system timing
requirements for data accesses.
Reading Data Using the FIFO
The ADPD1080/ADPD1081 include a 128-byte FIFO memory
buffer that can store data from either or both time slots.
Register 0x11 selects the kind of data from each time slot to be
written to the FIFO. Note that both time slots can use the FIFO,
but only if their output data rate is the same.
Output Data Rate = f
SAMPLE
/N
X
where:
f
SAMPLE
is the sampling frequency.
N
X
is the averaging factor for each time slot (N
A
for Time Slot A
and N
B
for Time Slot B). In other words, N
A
= N
B
must be true
to store data from both time slots in the FIFO.
Data packets are written to the FIFO at the output data rate. A
data packet for the FIFO consists of a complete sample for each
enabled time slot. Data for each photodiode channel can be stored
as either 16 or 32 bits. Each time slot can store 2, 4, 8, or 16 bytes of
data per sample, depending on the mode and data format. To
ensure that data packets are intact, new data is only written to
the FIFO if there is sufficient space for a complete packet. Any
new data that arrives when there is not enough space is lost.
The FIFO continues to store data when sufficient space exists.
Always read FIFO data in complete packets to ensure that data
packets remain intact.
The number of bytes currently stored in the FIFO is available in
Register 0x00, Bits[15:8]. A dedicated FIFO interrupt is also
available and automatically generates when a specified amount
of data is written to the FIFO.
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