Datasheet

ADPD1080/ADPD1081 Data Sheet
Rev. B | Page 28 of 74
I
2
C SERIAL INTERFACE
The ADPD1080 supports an I
2
C serial interface via the SDA
(data) and SCL (clock) pins. All internal registers are accessed
through the I
2
C interface. The ADPD1080 is an I
2
C only device
and does not support an SPI.
The ADPD1080 conforms to the UM10204 I
2
C-Bus Specification
and User Manual, Rev. 05—9 October 2012, available from NXP
Semiconductors. The I
2
C interface supports up to 1 Mbps data
transfers. Register read and write are supported, as shown in
Figure 32. Figure 3 shows the timing diagram for the I
2
C
interface.
Slave Address
The default 7-bit I
2
C slave address for the device is 0x64,
followed by the R/
W
bit. For a write, the default I
2
C slave
address is 0xC8; for a read, the default I
2
C address is 0xC9. The
slave address is configurable by writing to Register 0x09, Bits[7:1].
When multiple ADPD1080 devices are on the same bus lines,
the GPIO0 and GPIO1 pins can be used to select specific
devices for the address change. Register 0x0D can be used to
select a key to enable address changes in specific devices. Use
the following procedure to change the slave address when
multiple ADPD1080 devices are connected to the same I
2
C bus
lines:
1. Using Register 0x4F, enable the input buffer of the GPIO1 pin,
the GPIO0 pin, or both, depending on the key being used.
2. For the device identified as requiring an address change,
set the GPIO0 and/or GPIO1 pins high or low to match the
key being used.
3. Write the SLAVE_ADDRESS_KEY bits using Register 0x0D,
Bits[15:0] to match the desired function. The allowed keys
are shown in Table 42.
4. Write to the desired SLAVE_ADDRESS bits using
Register 0x09, Bits[7:1]. While writing to Register 0x09,
Bits[7:1], write 0xAD to Register 0x09, Bits[15:8]
(ADDRESS_WRITE_KEY). Register 0x09 must be
written to immediately after writing to Register 0x0D.
5. Repeat Step 1 to Step 4 for all the devices that need
SLAVE_ADDRESS changed.
6. Set the GPIO0 and GPIO1 pins as desired for normal
operation using the new SLAVE_ADDRESS for each device.
I
2
C Write and Read Operations
Figure 32 shows the ADPD1080 I
2
C write and read operations.
Single-word and multiword read operations are supported. For
a single register read, the host sends a no acknowledge (NACK)
after the second data byte is read and a new register address is
needed for each access.
For multiword operations, each pair of data bytes is followed by
an acknowledge from the host until the last byte of the last word
is read. The host indicates the last read word by sending a no
acknowledge. When reading from the FIFO_ACCESS
(Register 0x60), the data is automatically advanced to the next
word in the FIFO, and the space is freed. When reading from
other registers, the register address is automatically advanced to
the next register, except at Register 0x5F (DATA_ACCESS_CTL)
or Register 0x7F (B_PD4_HIGH), where the address does not
increment. This auto-incrementing allows lower overhead
reading of sequential registers.
All register writes are single word only and require 16 bits (one
word) of data.
The software reset, SW_RESET (Register 0x0F, Bit 0), returns
an acknowledge. The device then returns to standby mode with
all registers in the default state.
Table 19. Definitions of I
2
C Terminology
Term Description
SCL Serial clock.
SDA Serial address and data.
Master The master is the device that initiates a transfer, generates clock signals, and terminates a transfer.
Slave The slave is the device addressed by a master. The ADPD1080 operates as a slave device.
Start (S) A high to low transition on the SDA line while SCL is high; all transactions begin with a start condition.
Start (Sr) Repeated start condition.
Stop (P) A low to high transition on the SDA line while SCL is high. A stop condition terminates all transactions.
ACK During the acknowledge or no acknowledge clock pulse, the SDA line is pulled low and remains low.
NACK During the acknowledge or no acknowledge clock pulse, the SDA line remains high.
Slave Address After a start (S), a 7-bit slave address is sent, which is followed by a data direction bit (read or write).
Read (R) A 1 indicates a request for data.
Write (W) A 0 indicates a transmission.
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