Datasheet
ADPD1080/ADPD1081 Data Sheet
Rev. B | Page 24 of 74
STATE MACHINE OPERATION
During each time slot, the ADPD1080/ADPD1081 operate
according to a state machine. The state machine operates in the
sequence shown in Figure 27.
STANDBY
REGISTER 0x10 = 0x0000
ULTRALOW POWER MODE
NO DATA COLLECTION
ALL REGISTER VALUES ARE RETAINED.
PROGRAM
REGISTER 0x10 = 0x0001
SAFE MODE FOR PROGRAMING REGISTERS
NO DATA COLLECTION
DEVICE IS FULLY POWERED IN THIS MODE.
NORMAL OPERATION
REGISTER 0x10 = 0x0002
LEDs ARE PULSED AND PHOTODIODES ARE SAMPLED
STANDARD DATA COLLECTION
DEVICE POWER IS CYCLED BY INTERNAL STATE MACHINE.
16110-027
Figure 27. State Machine Operation Flowchart
The ADPD1080/ADPD1081 operate in one of three modes:
standby, program, and normal operation.
Standby mode is a power saving mode in which no data collection
occurs. All register values are retained in this mode. To place
the devices in standby mode, write 0x0 to Register 0x10,
Bits[1:0]. The devices power up in standby mode.
Program mode is used for programming registers. Always cycle
the ADPD1080/ADPD1081 through program mode when writing
registers or changing modes. Because no power cycling occurs in
this mode, the devices may consume higher current in program
mode than in normal operation. To place the devices in program
mode, write 0x1 to Register 0x10, Bits[1:0].
In normal operation, the ADPD1080/ADPD1081 pulse light
and collect data. Power consumption in this mode depends on
the pulse count and data rate. To place the devices in normal
sampling mode, write 0x2 to Register 0x10, Bits[1:0].
NORMAL MODE OPERATION AND DATA FLOW
In normal mode, the ADPD1080/ADPD1081 follow a specific
pattern set up by the state machine. This pattern is shown in the
corresponding datapath diagram shown in Figure 28. The pattern
is as follows:
1. LED pulse and sample. The ADPD1080/ADPD1081 pulse
external LEDs. The response of a photodiode or photodiodes
to the reflected light is measured by the ADPD1080/
ADPD1081. Each data sample is constructed from the sum
of n individual pulses, where n is user configurable between
1 and 255.
2. Intersample averaging. If desired, the logic can average
n samples, from 2 to 128 in powers of 2, to produce output
data. New output data is saved to the output registers every
N samples.
3. Data read. The host processor reads the converted results
from the data register or the FIFO.
4. Repeat. The sequence has a few different loops that enable
different types of averaging while keeping both time slots
close in time relative to each other.
SAMPLE 1: TIME SLOT B
16 BITS
[14 + LOG
2
(n
A
)] BITS
UP TO 20 BITS
[14 + LOG
2
(
n
A
× N
A
)] BITS
UP TO 27 BITS
[14 + LOG
2
(
n
B
× N
B
)] BITS
UP TO 27 BITS
TIME SLOT B
TIME SLOT A
16-BIT CLIP
IF VAL ≤ (2
16
– 1)
VAL = VAL
ELSE VAL = 2
16
– 1
NOTES
1. n
A
AND n
B
= NUMBER OF LED PULSES FOR TIME SLOT A AND TIME SLOT B.
2. N
A
AND N
B
= NUMBER OF AVERAGES FOR TIME SLOT A AND TIME SLOT B.
16 BITS
[14 + LOG
2
(n
B
)] BITS
UP TO 20 BITS
16-BIT CLIP
IF VAL ≤ (2
16
– 1)
VAL = VAL
ELSE VAL = 2
16
– 1
1
N
B
ADC OFFSET
[14 + LOG
2
(n
A
)] BITS
UP TO 22 BITS
SAMPLE 1: TIME SLOT A
SAMPLE N
B
: TIME SLOT B
SAMPLE N
A
: TIME SLOT A
14 BITS
14 BITS
20-BIT CLIP
IF VAL ≤ (2
20
– 1)
VAL = VAL
ELSE VAL = 2
20
– 1
n
A
n
A
14-BIT
ADC
1
n
A
1
N
A
FIFO
32-BIT DATA
REGISTERS
16-BIT
DATA
REGISTERS
16110-028
0 1
0 1
REGISTER
0x11[13]
÷ N
A
÷ N
A
Figure 28. ADPD1080/ADPD1081 Datapath
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