Datasheet

Data Sheet ADPD1080/ADPD1081
Rev. B | Page 23 of 74
ADJUSTABLE SAMPLING FREQUENCY
Register 0x12 controls the sampling frequency setting of the
ADPD1080/ADPD1081 and Register 0x4B, Bits[5:0] further
tunes this clock for greater accuracy. An internal 32 kHz sample
rate clock that also drives the transition of the internal state
machine governs the sampling frequency. The maximum
sampling frequencies for some sample conditions are listed in
Table 3. The maximum sample frequency for all conditions is
determined by the following equation:
f
SAMPLE, MAX
= 1/(t
A
+ t
1
+ t
B
+ t
2
+ t
SLEEP, MIN
)
where t
S L EE P, M I N
is the minimum sleep time required between
samples. See Table 15.
If a given time slot is not in use, elements from that time slot do
not factor into the calculation. For example, if Time Slot A is
not in use, t
A
and t
1
do not add to the sampling period and the
new maximum sampling frequency is calculated as follows:
f
SAMPLE, MAX
= 1/(t
B
+ t
2
+ t
SLEEP, MIN
)
See the Dual Time Slot Operation section for the definitions of
t
A
, t
1
, t
B
, and t
2
. The maximum achievable sampling rate with a
single pulse in Time Slot B is ~2.8 kSPS.
External Sync for Sampling
The ADPD1080/ADPD1081 provide an option to use an
external sync signal to trigger the sampling periods. This
external sample sync signal can be provided either on the
GPIO0 pin or the GPIO1 pin. This functionality is controlled
by Register 0x4F, Bits[3:2]. When enabled, a rising edge on the
selected input specifies when the next sample cycle occurs.
When triggered, there is a delay of one to two internal sampling
clock (32 kHz) cycles, and then the normal start-up sequence
occurs. This sequence is the same when the normal sample
timer provides the trigger. To enable the external sync signal
feature, use the following procedure:
1. Write 0x1 to Register 0x10 to enter program mode.
2. Write the appropriate value to Register 0x4F, Bits[3:2] to
select whether the GPIO0 pin or the GPIO1 pin specifies
when the next sample cycle occurs. Also, enable the
appropriate input buffer using Register 0x4F, Bit 1, for the
GPIO0 pin, or Register 0x4F, Bit 5, for the GPIO1 pin.
3. Write 0x4000 to Register 0x38.
4. Write 0x2 to Register 0x10 to start the sampling operations.
5. Apply the external sync signal on the selected pin at the
desired rate; sampling occurs at that rate. As with normal
sampling operations, read the data using the FIFO or the
data registers.
The maximum frequency constraints also apply in this case.
Providing an External 32 kHz Clock
The ADPD1080/ADPD1081 have an option for the user to
provide an external 32 kHz clock to the devices for system
synchronization or for situations where a clock with better
accuracy than the internal 32 kHz clock is required. The
external 32 kHz clock is provided on the GPIO1 pin. To enable
the 32 kHz external clock, use the following procedure at startup:
1. Drive the GPIO1 pin to a valid logic level or with the
desired 32 kHz clock prior to enabling the GPIO1 pin as an
input. Do not leave the pin floating prior to enabling it.
2. Write 01 to Register 0x4F, Bits[6:5] to enable the GPIO1 pin as
an input.
3. Write 10 to Register 0x4B, Bits[8:7] to configure the devices to
use an external 32 kHz clock. This setting disables the
internal 32 kHz clock and enables the external 32 kHz clock.
4. Write 0x1 to Register 0x10 to enter program mode.
5. Write additional control registers in any order while the
devices are in program mode to configure the devices as
required.
6. Write 0x2 to Register 0x10 to start the normal sampling
operation.
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