Datasheet

ADP8866 Data Sheet
Rev. A | Page 4 of 52
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Thermal Shutdown
Threshold TSD Increasing temperature 150 °C
Hysteresis TSD
(HYS)
20 °C
Isolation from Input to
Output During Fault
I
OUTLKG
V
IN
= 5.5 V, V
OUT
= 0 V, Bit nSTBY = 0 1 μA
Time to Validate a Fault t
FAU LT
2 μs
I
2
C INTERFACE
V
DDIO
Voltage Operating Range V
DDIO
5.5 V
Logic Low Input V
IL
V
IN
= 2.5 V 0.5 V
Logic High Input V
IH
V
IN
= 5.5 V 1.55 V
I
2
C TIMING SPECIFICATIONS Guaranteed by design
Delay from Reset Deassertion
to I
2
C Access
t
RESET
20 μs
SCL Clock Frequency f
SCL
400 kHz
SCL High Time t
HIGH
0.6 μs
SCL Low Time t
LOW
1.3 μs
Setup Time
Data t
SU, DAT
100 ns
Repeated Start t
SU, STA
0.6 μs
Stop Condition t
SU, STO
0.6 μs
Hold Time
Data t
HD, DAT
0 0.9 μs
Start/Repeated Start t
HD, STA
0.6 μs
Bus Free Time (Stop and Start
Conditions)
t
BUF
1.3 μs
Rise Time (SCL and SDA) t
R
20 + 0.1 × C
B
300 ns
Fall Time (SCL and SDA) t
F
20 + 0.1 × C
B
300 ns
Pulse Width of Suppressed
Spike
t
SP
0 50 ns
Capacitive Load Per Bus Line C
B
400 pF
Timing Diagram
SDA
SCL
S
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Sr P S
t
LOW
t
R
t
HD, DAT
t
HIGH
t
SU, DAT
t
F
t
F
t
SU, STA
t
HD, STA
t
SP
t
SU, STO
t
BUF
t
R
09478-002
Figure 2. I
2
C Interface Timing Diagram