Datasheet

ADP8863
Rev. A | Page 4 of 52
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FAULT PROTECTION
Start-Up Charging Current Source I
SS
V
IN
= 3.6 V, V
OUT
= 0.8 × V
IN
2.5 3.75 5.5 mA
Output Voltage Threshold V
OUT
Exit Soft Start V
OUT(START)
V
OUT
rising 0.92 × V
IN
V
Short-Circuit Protection V
OUT(SC)
V
OUT
falling 0.55 × V
IN
V
Output Overvoltage Protection V
OVP
Activation Level 5.8 V
OVP Recovery Hysteresis V
OVP(HYS)
500 mV
Thermal Shutdown
Threshold TSD 150 °C
Hysteresis TSD
(HYS)
20 °C
Isolation from Input to Output
During Fault
I
OUTLKG
V
IN
= 5.5 V, V
OUT
= 0 V, Bit nSTBY = 0 1.5 A
Time to Validate a Fault t
FAU LT
2 s
I
2
C INTERFACE
Operating V
DDIO
Voltage V
DDIO
5.5 V
Logic Low Input
2
V
IL
V
IN
= 3.6 V 0.6 V
Logic High Input
3
V
IH
V
IN
= 3.6 V 1.30 V
I
2
C TIMING SPECIFICATIONS Guaranteed by design
Delay from Reset Deassertion to
I
2
C Access
t
RESET
20 s
SCL Frequency f
SCL
400 kHz
SCL High Time t
HIGH
0.6 s
SCL Low Time t
LOW
1.3 s
Setup Time
Data t
SU, DAT
100 ns
Repeated Start t
SU, STA
0.6 s
Stop Condition t
SU, STO
0.6 s
Hold Time
Data t
HD, DAT
0 0.9 s
Start/Repeated Start t
HD, STA
0.6 s
Bus Free Time (Stop and Start
Conditions)
t
BUF
1.3 s
Rise Time (SCL and SDA) t
R
20 + 0.1 C
B
300 ns
Fall Time (SCL and SDA) t
F
20 + 0.1 C
B
300 ns
Pulse Width of Suppressed Spike t
SP
0 50 ns
Capacitive Load per Bus Line C
B
400 pF
1
Current source matching is calculated by dividing the difference between the maximum and minimum current from the sum of the maximum and minimum.
2
V
IL
is a function of the input voltage. See in the section for typical values over operating ranges. Figure 16
Figure 16
Typical Performance Characteristics
Typical Performance Characteristics
3
V
IH
is a function of the input voltage. See in the section for typical values over operating ranges.
I
2
C TIMING DIAGRAM
S
D
A
SCL
S
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Sr
P S
t
LOW
t
R
t
HD, DAT
t
HIGH
t
SU, DAT
t
F
t
F
t
SU, STA
t
HD, STA
t
SP
t
SU, STO
t
BUF
t
R
08392-002
Figure 2. I
2
C Interface Timing Diagram