Datasheet

ADP8863
Rev. A | Page 28 of 52
Mode Control Register 2 (MDCR2)—Register 0x02
Table 13. MDCR2 Bit Map
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved SHORT_INT TSD_INT OVP_INT CMP2_INT CMP_INT
Table 14. Bit Descriptions for the MDCR2 Register
Bit Name Bit No. Description
1
N/A [7:5] Reserved.
SHORT_INT 4 Short-circuit error interrupt.
1 = a short-circuit or overload condition on VOUT has been detected.
0 = no short-circuit or overload condition has been detected.
TSD_INT 3 Thermal shutdown interrupt.
1 = the device temperature has exceeded 150°C (typical).
0 = no overtemperature condition has been detected.
OVP_INT 2 Overvoltage interrupt.
1 = VOUT has exceeded V
OVP
.
0 = VOUT has not exceeded V
OVP
.
CMP2_INT 1 1 = the second ALS comparator (CMP_IN2) has changed state.
0 = the second sensor comparator has not been triggered.
CMP_INT 0 1 = main ALS comparator (CMP_IN) has changed state.
0 = the main sensor comparator has not been triggered.
1
Interrupt bits are cleared by writing a 1 to the flag; writing a 0 or reading the flag has no effect.
Interrupt Enable (INTR_EN)—Register 0x03
Table 15. INTR_EN Bit Map
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved SHORT_IEN TSD_IEN OVP_IEN CMP2_IEN CMP_IEN
Table 16. Bit Descriptions for the INTR_EN Register
Bit Name Bit No. Description
N/A [7:5] Reserved.
SHORT_IEN 4
Short-circuit interrupt is enabled. When the SHORT_INT status bit is set after an error condition, an interrupt is
raised to the host if the SHORT_IEN flag is enabled.
1 = the short-circuit interrupt is enabled.
0 = the short-circuit interrupt is disabled (the SHORT_INT flag continues to assert).
TSD_IEN 3
Thermal shutdown interrupt is enabled. When the TSD_INT status bit is set after an error condition, an interrupt is
raised to the host if the TSD_IEN flag is enabled.
1 = the thermal shutdown interrupt is enabled.
0 = the thermal shutdown interrupt is disabled (the TSD_INT flag continues to assert).
OVP_IEN 2
Overvoltage interrupt enabled. When the OVP_INT status bit is set after an error condition, an interrupt is raised to
the host if the OVP_IEN flag is enabled.
1 = the overvoltage interrupt is enabled.
0 = the overvoltage interrupt is disabled (the OVP_INT flag continues to assert).
CMP2_IEN 1
When the CMP2_INT status bit is set after an enabled comparator trips, an interrupt is raised if the CMP2_IEN flag is
enabled.
1 = the second phototransistor comparator interrupt is enabled.
0 = the second phototransistor comparator interrupt is disabled (the CMP2_INT flag continues to assert).
CMP_IEN 0
When the CMP_INT status bit is set after an enabled comparator trips, an interrupt is raised if the CMP_IEN flag is
enabled.
1 = the main comparator interrupt is enabled.
0 = the main comparator interrupt is disabled (the CMP_INT flag continues to assert).