Datasheet
ADP8860
Rev. 0 | Page 28 of 52
Manufacturer and Device ID (MFDVID)—Register 0x00
This is a read-only register.
Table 9. MFDVID Manufacturer and Device ID Bit Map
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Manufacture ID Device ID
0 0 0 0 0 1 1 1
Mode Control Register (MDCR)—Register 0x01
Table 10. MDCR Mode Control Bit Map
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved INT_CFG nSTBY DIM_EN Reserved SIS_EN CMP_AUTOEN BL_EN
Table 11. Bit Descriptions for the MDCR Register
Bit Name Bit No. Description
N/A 7 Reserved.
INT_CFG 6 Interrupt configuration.
1 = processor interrupt deasserts for 50 μs and reasserts with pending events.
0 = processor interrupt remains asserted if the host tries to clear the interrupt while there is a pending event.
nSTBY 5 1 = device is in active mode.
0 = device is in standby mode, only the I
2
C interface is enabled.
DIM_EN 4 DIM_EN is set by the hardware after a DIM timeout. The user may also force the backlight into DIM mode by
asserting this bit. DIM mode can only be entered if BL_EN is also enabled.
1 = backlight is operating at the DIM current level (BL_EN must also be asserted).
0 = backlight is not in DIM mode.
N/A 3 Reserved.
SIS_EN 2 Synchronous independent sinks enable.
1 = enables all LED current sinks designated as independent sinks. All of the ISC enable bits must be cleared; if
any of the SC_EN bits in Register 0x10 are set, this bit has no effect.
0 = disables all sinks designated as independent sinks. All of the ISC enable bits must be cleared; if any of the
SC_EN bits are set in Register 0x10, this bit has no effect.
CMP_AUTOEN 1 1 = backlight automatically responds to the comparator outputs (L2_OUT and L3_OUT). L2_EN and/or L3_EN
must be set for this to function. BLV values in Register 0x04 are overridden.
0 = backlight does not autorespond to comparator level changes. The user can manually select backlight
operating levels using Bit BLV in Register 0x04.
BL_EN 0 1 = backlight is enabled (nSTBY must also be asserted).
0 = backlight is disabled.