Datasheet

Data Sheet ADP7182
Rev. C | Page 27 of 28
OUTLINE DIMENSIONS
PIN 1
INDIC
ATOR
(R 0.2)
BOTTOM VIEW
T
OP
VIEW
1
4
8
5
INDEX
ARE
A
SEA
TING
PLANE
0.80
0.75
0.70
0.30
0.25
0.18
0.05 MAX
0.02 NOM
0.80 MAX
0.55 NOM
0.20 REF
0.50 BSC
COPLANARITY
0.08
2.48
2.38
2.23
1.74
1.64
1.49
0.50
0.40
0.30
COMPLIANT TO
JEDEC STANDARDS MO-229-WEED-4
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-B
0.20 MIN
EXPOSED
PAD
3.10
3.00 SQ
2.90
Figure 97. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-5)
Dimensions shown in millimeters
100708-A
*
COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
1.60 BSC
2.80 BSC
1.90
BSC
0.95 BSC
0.20
0.08
0.60
0.45
0.30
8°
4°
0°
0.50
0.30
0.10 MAX
*
1.00 MAX
*
0.90 MAX
0.70 MIN
2.90 BSC
5 4
1 2 3
SEATING
PLANE
Figure 98. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters