Datasheet

Data Sheet ADP7182
Rev. C | Page 21 of 28
APPLICATIONS INFORMATION
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CAPACITOR SELECTION
Output Capacitor
The ADP7182 is designed for operation with small space-saving
ceramic capacitors; however, it functions with most commonly
used capacitors as long as care is taken with regard to the ESR
value. The ESR of the output capacitor affects the stability of the
LDO control loop. A minimum of 2.2 µF capacitance with an
ESR of 0.2 Ω or less is recommended to ensure the stability of
the ADP7182. Transient response to changes in load current is
also affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADP7182
to large changes in load current. Figure 78 shows the transient
responses for an output capacitance value of 2.2 µF.
CH1 100mA
B
W
CH2 50mV
B
W
M40µs
A CH1 –122mA
T 10.60%
1
2
T
10703-078
V
OUT
LOAD CURRENT
Figure 78. Output Transient Response, C
OUT
= 2.2 µF
Input Bypass Capacitor
Connecting a 2.2 µF capacitor from VIN to GND reduces the
circuit sensitivity to PCB layout, especially when long input
traces or high source impedance are encountered. When more
than 2.2 µF of output capacitance is required, increase the input
capacitance to match it.
Input and Output Capacitor Properties
As long as they meet the minimum capacitance and maximum
ESR requirements, any good quality ceramic capacitors can be
used with the ADP7182. Ceramic capacitors are manufactured
with a variety of dielectrics, each with different behavior over
temperature and applied voltage. Capacitors must have a dielectric
adequate to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 25 V or 50 V are recommended. Due to
their poor temperature and dc bias characteristics, Y5V and Z5U
dielectrics are not recommended.
Figure 79 depicts the capacitance vs. voltage bias characteristics
of an 0805, 2.2 µF, 25 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is ~ ±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
2.5
0
0.5
1.0
1.5
2.0
0 5
10 15 20 25
30
CAPACITANCE (µF)
DC BIAS (V)
10703-079
Figure 79. Capacitance vs. DC Bias Characteristics
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance,
and voltage.
C
EFF
= C
BIAS
× (1 − TEMPCO) × (1 − TOL) (1)
where:
C
BIAS
is the effective capacitance at the operating voltage, which
is −3 V for this example.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is 15% for an X5R dielectric. The tolerance
of the capacitor (TOL) is 10%, and the C
BIAS
is 2.08 µF at a 3 V bias,
as shown in Figure 79.
Substituting these values in Equation 1 yields
C
EFF
= 2.08 μF × (1 − 0.15) × (1 − 0.1) = 1.59 µF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage of −3 V.
To guarantee the performance of the ADP7182, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.