Datasheet

ADP7182 Data Sheet
Rev. C | Page 20 of 28
THEORY OF OPERATION
The ADP7182 is a low quiescent current, LDO linear regulator
that operates from −2.7 V to −28 V and can provide up to −200 mA
of output current. Drawing a low −650 µA of quiescent current
(typical) at full load makes the ADP7182 ideal for battery-powered
portable equipment. Maximum shutdown current consumption
is −8 µA at room temperature.
Optimized for use with small 2.2 µF ceramic capacitors, the
ADP7182 provides excellent transient performance.
VOUT
GND
EN
VIN
REFERENCE
SHUTDOWN
R2
R1
SHORT
CIRCUIT
THERMAL
PROTECT
VREG
10703-075
Figure 75. Fixed Output Voltage Internal Block Diagram
VOUT
ADJ
GND
EN
VIN
–1.22V
REFERENCE
SHUTDOWN
SHORT
CIRCUIT
THERMAL
PROTECT
VREG
10703-076
Figure 76. Adjustable Output Voltage Internal Block Diagram
Internally, the ADP7182 consists of a reference, an error amplifier,
a feedback voltage divider, and an NMOS pass transistor.
Output current is delivered via the NMOS pass transistor,
which is controlled by the error amplifier. The error amplifier
compares the reference voltage with the feedback voltage from
the output and amplifies the difference. If the feedback voltage is
more positive than the reference voltage, the gate of the NMOS
transistor is pulled toward GND, allowing more current to pass
and increasing the output voltage. If the feedback voltage is more
negative than the reference voltage, the gate of the NMOS
transistor is pulled toward −V
IN
, allowing less current to pass
and decreasing the output voltage.
The ESD protection devices are shown in the block diagram as
Zener diodes (see Figure 75 and Figure 76).
ENABLE PIN OPERATION
The ADP7182 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. When EN is at ±2 V with
respect to GND, VOUT turns on, and when EN is at 0 V, VO U T
turns off. For automatic startup, EN can be connected to VIN.
ADJUSTABLE MODE OPERATION
The ADP7182 is available in a fixed output voltage and an
adjustable mode version with an output voltage that can be set
to between −1.22 V and −27 V by an external voltage divider. The
output voltage can be set according to
−V
OUT
= −1.22 V (1 + R
FB1
/R
FB2
)
R
FB2
must be less than 120 kΩ to minimize the output voltage errors
due to the leakage current of the ADJ pin. The error voltage
caused by the ADJ pin leakage current is the parallel combination
of R
FB1
and R
FB2
times the ADJ pin leakage current.
For example, when R
FB1
= R
FB2
= 120 kΩ, the output voltage is
−2.44 V and the error due to the typical ADJ pin leakage current
(10 nA) is 60 kΩ times 10 nA, or 6 mV. This example results in
an output voltage error of 0.245%.
The addition of a small capacitor (~100 pF) in parallel with
R
FB1
can improve the stability of the ADP7182. Larger values of
capacitance also reduce the noise and improve PSRR (see the
Noise Reduction of the Adjustable ADP7182 section).
R
FB2
120kΩ
R
FB1
120kΩ
GND
EN
ADJ
VIN VOUT
ADP7182
ON
ON
–2V
OFF 0V
2V
V
IN
= –3V V
OUT
= –2.44V
C
OUT
2.2µF
C
IN
2.2µF
10703-077
Figure 77. Setting Adjustable Output Voltage