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–28 V, −200 mA, Low Noise, Linear

Regulator

Data Sheet

ADP7182

Rev. C Document Feedback

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FEATURES

Low noise: 18 µV rms

Power supply rejection ratio (PSRR): 66 dB at 10 kHz at V

OUT

= −3 V

Positive or negative enable logic

Stable with small 2.2 µF ceramic output capacitor

Input voltage range: −2.7 V to −28 V

Maximum output current: −200 mA

Low dropout voltage: −185 mV at −200 mA load

Initial accuracy: ±1%

Accuracy over line, load, and temperature

+2% maximum/−3% minimum

Low quiescent current, I

GND

= −650 µA with −200 mA load

Low shutdown current: −2 µA

Adjustable output from −1.22 V to −V

+ V

Current-limit and thermal overload protection

8-lead LFCSP and 5-lead TSOT

APPLICATIONS

Regulation to noise sensitive applications

Analog-to-digital converter (ADC) and digital-to-analog

converter (DAC) circuits, precision amplifiers

Communications and infrastructure

Medical and healthcare

Industrial and instrumentation

TYPICAL APPLICATION CIRCUITS

GND

VIN

VOUT

ADP7182

–2V

OFF 0V

= –8V V

OUT

= –5V

OUT

2.2µF

10703-001

Figure 1. ADP7182 with Fixed Output Voltage, V

OUT

= −5 V

13kΩ

40.2kΩ

GND

EN ADJ

VIN VOUT

ADP7182

–2V

OFF 0V

= –8V V

OUT

= –5V

OUT

2.2µF

10703-002

Figure 2. ADP7182 with Adjustable Output Voltage, V

OUT

= −5 V

GENERAL DESCRIPTION

The ADP7182 is a CMOS, low dropout (LDO) linear regulator

that operates from −2.7 V to −28 V and provides up to −200 mA

of output current. This high input voltage LDO is ideal for

regulation of high performance analog and mixed signal circuits

operating from −27 V down to −1.22 V rails. Using an advanced

proprietary architecture, it provides high power supply rejection

and low noise, and achieves excellent line and load transient

response with a small 2.2 µF ceramic output capacitor.

The ADP7182 is available in a fixed output voltage and an

adjustable version that allows the output voltage to range from

−1.22 V to −V

+ V

via an external feedback divider.

The ADP7182 regulator output noise is 18 µV rms independent

of the output voltage. The enable logic is capable of interfacing

with positive or negative logic levels for maximum flexibility.

The ADP7182 is available in 5-lead TSOT and 8-lead LFCSP

packages for a small, low profile footprint.

Summary of content (28 pages)

PAGE 1
–28 V, −200 mA, Low Noise, Linear Regulator ADP7182 Data Sheet FEATURES TYPICAL APPLICATION CIRCUITS GND VIN = –8V ON OFF –2V VIN VOUT = –5V VOUT ADP7182 2V EN 0V NC ON Figure 1. ADP7182 with Fixed Output Voltage, VOUT = −5 V CIN 2.2µF COUT 2.2µF GND ON OFF VIN 2V 0V VOUT 13kΩ 40.2kΩ VOUT = –5V ADP7182 EN ADJ ON 10703-002 VIN = –8V –2V APPLICATIONS COUT 2.2µF CIN 2.
PAGE 2
ADP7182 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 20 Applications ....................................................................................... 1 Enable Pin Operation ................................................................ 20 Typical Application Circuits.................................................
PAGE 3
Data Sheet ADP7182 SPECIFICATIONS VIN = (VOUT − 0.5 V) or −2.7 V (whichever is greater), EN = VIN, IOUT = −10 mA, CIN = COUT = 2.2 µF, TJ = −40°C to +125°C for minimum/maximum specifications, TA = 25°C for typical specifications, unless otherwise noted. Table 1.
PAGE 4
ADP7182 Parameter POWER SUPPLY REJECTION RATIO Data Sheet Symbol PSRR Test Conditions/Comments 1 MHz, VIN = −4.3 V, VOUT = −3 V 1 MHz, VIN = −6 V, VOUT = −5 V 100 kHz, VIN = −4.3 V, VOUT = −3 V 100 kHz, VIN = −6 V, VOUT = −5 V 10 kHz, VIN = −4.
PAGE 5
Data Sheet ADP7182 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN to GND VOUT to GND EN to GND EN to VIN ADJ to GND Storage Temperature Range Operating Junction Temperature Range Operating Ambient Temperature Range Soldering Conditions Rating +0.3 V to −30 V 0.3 V to VIN 5 V to VIN +30 V to −0.3 V +0.3 V to VOUT −65°C to +150°C −40°C to +125°C −40°C to +85°C JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 6
ADP7182 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 5 VOUT GND 1 VIN 2 TOP VIEW (Not to Scale) EN 3 VOUT 4 EN 3 NC 4 ADJ NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. TOP VIEW (Not to Scale) 10703-003 VIN 2 5 ADP7182 ADP7182 10703-004 GND 1 Figure 3. 5-Lead TSOT Pin Configuration, Fixed Output Voltage Figure 4. 5-Lead TSOT Pin Configuration, Adjustable Output Voltage Table 5. 5-Lead TSOT Pin Function Descriptions TSOT Pin No.
PAGE 7
Data Sheet ADP7182 NC 3 TOP VIEW (Not to Scale) EXPOSED PAD EN 4 VOUT 1 7 VIN VOUT 2 ADJ 3 6 GND 5 NC EN 4 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO VIN INSIDE THE PACKAGE. THE EXPOSED PAD MUST BE CONNECTED TO THE VIN PLANE ON THE BOARD FOR PROPER OPERATION. BECAUSE THIS IS A NEGATIVE VOLTAGE REGULATOR, VIN IS THE MOST NEGATIVE POTENTIAL IN THE CIRCUIT.
PAGE 8
ADP7182 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VIN = −3.5 V, VOUT = −3 V, IOUT = −10 mA, CIN = COUT = 2.2 µF, TA = 25°C, unless otherwise noted. –2.980 VOUT (V) –2.985 0 = –100µA = –1mA = –10mA = –50mA = –100mA = –200mA –100 –2.990 –2.995 –3.000 –3.005 –200 –300 –400 ILOAD ILOAD ILOAD ILOAD ILOAD ILOAD –500 –600 –3.010 = –100µA = –1mA = –10mA = –50mA = –100mA = –200mA –700 –3.015 –40 –5 25 85 –800 10703-007 –3.020 125 JUNCTION TEMPERATURE (°C) –40 –5 25 85 10703-010 –2.
PAGE 9
Data Sheet ADP7182 0 0 –0.5 –200 GROUND CURRENT (µA) –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 –5.0 –50 VIN = –2.7V VIN = –3.0V VIN = –4.0V VIN = –5.0V VIN = –8.0V VIN = –28.0V –25 –400 –600 –800 –1000 0 25 50 75 100 125 –1200 –3.4 TEMPERATURE (°C) –3.2 –3.0 –2.8 Figure 16. Ground Current vs. Input Voltage (VIN) in Dropout 0 –4.90 –4.92 –40 –4.94 –60 –4.96 –80 –4.98 –100 –120 –5.00 –5.02 –140 –5.04 –160 –5.06 –180 –5.08 –200 1 10 100 1000 ILOAD (mA) –5.10 125 –5.
PAGE 10
ADP7182 Data Sheet 0 –4.97 –100 –5.01 –300 –400 –500 –600 –5.02 –700 –25 –20 –15 –10 –5 –800 –30 10703-019 –5.03 –30 0 VIN (V) –100 –20 –200 –40 DROPOUT VOLTAGE (mV) –300 –400 ILOAD = –50mA ILOAD = –100mA ILOAD = –200mA –10 –5 0 –60 –80 –100 –120 –140 –700 –40 –5 25 85 –160 10703-020 –800 125 JUNCTION TEMPERATURE (°C) 1 10 100 1000 ILOAD (mA) Figure 20. Ground Current vs. Junction Temperature (TJ), VOUT = −5 V Figure 23. Dropout Voltage vs.
PAGE 11
Data Sheet ADP7182 0 –1.780 –200 –1.790 VOUT (V) –600 –800 –1.800 = –5mA = –10mA = –25mA = –50mA = –100mA = –200mA –1.805 –5.2 –5.0 –4.8 VIN (V) Figure 25. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = −5 V –1.810 –30 –1.780 –20 –15 –10 –5 0 Figure 28. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −1.8 V 0 = –100µA = –1mA = –10mA = –50mA = –100mA = –200mA –100 GROUND CURRENT (µA) –1.775 –25 VIN (V) –1.
PAGE 12
ADP7182 Data Sheet 0 –1.20 –100 –400 ILOAD = –50mA ILOAD = –100mA ILOAD = –200mA ILOAD = –100µA ILOAD = –1mA ILOAD = –10mA –500 –1.22 –1.23 –1.24 –600 –25 –20 –15 –10 –5 0 VIN (V) –1.25 –30 10703-031 –700 –30 Figure 31. Ground Current vs. Input Voltage (VIN), VOUT = −1.8 V ILOAD ILOAD ILOAD ILOAD ILOAD ILOAD = –100µA = –1mA = –10mA = –50mA = –100mA = –200mA –25 –20 –15 –10 –5 0 VIN (V) 10703-034 –300 VOUT (V) GROUND CURRENT (µA) –1.21 –200 Figure 34.
PAGE 13
Data Sheet ADP7182 –14.80 0 –14.85 –100 –14.95 –400 –15.00 –15.05 –15.10 –15.15 –500 –15.20 –700 –30 ILOAD = –100µA ILOAD = –1mA ILOAD = –10mA –25 –20 ILOAD = –50mA ILOAD = –100mA ILOAD = –200mA –15 –15.25 –10 –5 0 VIN (V) –15.30 –30 10703-037 –600 ILOAD ILOAD ILOAD ILOAD ILOAD ILOAD = –100µA = –1mA = –10mA = –50mA = –100mA = –200mA –25 –20 –15 VIN (V) Figure 37. Ground Current vs. Input Voltage (VIN), VOUT = −1.22 V Figure 40. Output Voltage (VOUT) vs.
PAGE 14
Data Sheet 0 0 –100 –200 –200 –400 GROUND CURRENT (µA) –300 –400 –500 ILOAD = –100µA ILOAD = –1mA ILOAD = –10mA –600 ILOAD = –50mA ILOAD = –100mA ILOAD = –200mA –20 –15 –800 –1000 –1200 VIN (V) –1600 –15.0 10703-043 –25 –600 Figure 43. Ground Current vs. Input Voltage (VIN), Adjustable Output Voltage, VOUT = −15 V –14.8 –14.6 –14.4 –14.2 –14.0 VIN (V) Figure 46. Ground Current vs.
PAGE 15
Data Sheet ADP7182 –20 PSRR (dB) –40 –60 –60 –70 –70 1.5 2.5 2.0 3.0 3.5 4.5 4.0 5.0 Figure 49. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage, VOUT = −1.22 V, Load Current (ILOAD) = −200 mA 0 –10 –20 ILOAD ILOAD ILOAD ILOAD –80 1.
PAGE 16
ADP7182 Data Sheet 0 0 FREQUENCY = 100Hz FREQUENCY = 1kHz FREQUENCY = 10kHz FREQUENCY = 100kHz FREQUENCY = 1MHz FREQUENCY = 10MHz –10 –20 FREQUENCY = 100Hz FREQUENCY = 1kHz FREQUENCY = 10kHz FREQUENCY = 100kHz FREQUENCY = 1MHz FREQUENCY = 10MHz –10 –20 PSRR (dB) PSRR (dB) –30 –40 –50 –30 –40 –50 –60 –60 –70 0 0.5 1.5 1.0 2.0 2.5 3.5 3.0 4.0 HEADROOM VOLTAGE (V) Figure 55. Power Supply Rejection Ratio (PSRR) vs.
PAGE 17
Data Sheet ADP7182 1 1 T T VOUT 2 VOUT 2 VIN CH2 2mV B W M10µs A CH3 T 10.00% 2.52V CH1 500mV BW Figure 61. Line Transient Response, 500 mV Step, VOUT = −1.22 V, ILOAD = −200 mA CH2 5mV B W M2µs A CH3 T 10.00% 1.60V 10703-064 CH1 500mV BW 10703-061 VIN Figure 64. Line Transient Response, 500 mV Step, VOUT = −1.8 V, ILOAD = −10 mA 1 1 T T VOUT 2 VIN VIN VOUT CH2 1mV B W M10µs A CH3 T 10.00% 2.52V CH1 1V BW Figure 62. Line Transient Response, 500 mV Step, VOUT = −1.
PAGE 18
ADP7182 Data Sheet 1 T T 1 VIN VOUT VIN VOUT CH1 1V BW CH2 10mV B W M2µs A CH3 T 10.00% 2.02V 10703-067 2 CH1 1V BW Figure 67. Line Transient Response, 500 mV Step, VOUT = −5 V, ILOAD = −200 mA CH2 2mV B M10µs A CH3 T 10.00% W 2.52V 10703-070 2 Figure 70. Line Transient Response, 500 mV Step, VOUT = −15 V, Noise Reduction Network, ILOAD = −10 mA 1 T T VOUT 2 VOUT 2 1 VIN CH2 5mV B W M2µs A CH3 T 10.00% 2.02V CH1 100mA BW CH2 50mV Figure 68.
PAGE 19
Data Sheet ADP7182 T T VOUT VOUT 2 2 1 1 CH2 50mV B W M10µs A CH1 T 10.00% –122mA 10703-073 CH1 100mA BW CH1 100mA BW CH2 50mV B W M40µs A CH1 T 10.00% Figure 73. Load Transient Response, VOUT = −5 V, ILOAD = −1 mA to −200 mA, Load Step = 1 A/µs –122mA 10703-074 LOAD CURRENT LOAD CURRENT Figure 74. Load Transient Response, VOUT = −15 V, ILOAD = −1 mA to −200 mA, Load Step = 1 A/µs, Noise Reduction Network Rev.
PAGE 20
ADP7182 Data Sheet THEORY OF OPERATION The ADP7182 is a low quiescent current, LDO linear regulator that operates from −2.7 V to −28 V and can provide up to −200 mA of output current. Drawing a low −650 µA of quiescent current (typical) at full load makes the ADP7182 ideal for battery-powered portable equipment. Maximum shutdown current consumption is −8 µA at room temperature. Optimized for use with small 2.2 µF ceramic capacitors, the ADP7182 provides excellent transient performance. R2 −VOUT = −1.
PAGE 21
Data Sheet ADP7182 APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL The ADP7182 is supported by the ADIsimPower™ design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic, bill of materials, and calculate performance in minutes.
PAGE 22
ADP7182 Data Sheet ENABLE PIN OPERATION T EN The ADP7182 provides a dual polarity enable pin (EN) that turns on the LDO when |VEN| ≥ 2 V. The enable voltage can be positive or negative with respect to ground. 1 0 VOUT 2 –1.0 CH1 500mV BW –1.5 CH2 500mV BW M40µs A CH1 T 10.20% 10703-082 VOUT (V) –0.5 590mV Figure 82. Typical Start-Up Behavior, Positive Going Enable VOUT WITH RISING VEN –1.5 –1.0 –0.5 1 0 0.5 1.0 1.5 ENABLE VOLTAGE (V) 10703-080 –2.0 –2.
PAGE 23
Data Sheet ADP7182 NOISE REDUCTION OF THE ADJUSTABLE ADP7182 CNR is chosen by setting the reactance of CNR equal to RFB1 − RNR at a frequency between 10 Hz and 100 Hz. This capacitance sets the frequency where the ac gain of the error amplifier is 3 dB down from its dc gain. COUT 2.2µF CIN 2.2µF GND ON OFF –2V VIN 2V 0V VOUT RFB1 147kΩ RNR 13kΩ CNR 100nF VOUT = –15V ADP7182 EN ADJ ON 10703-085 VIN = –16V RFB2 13kΩ Figure 85.
PAGE 24
ADP7182 Data Sheet THERMAL CONSIDERATIONS In most applications, the ADP7182 does not dissipate much heat due to its high efficiency. However, in applications with high ambient temperature, and high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125°C. When the junction temperature exceeds 150°C, the converter enters thermal shutdown.
PAGE 25
ADP7182 140 120 120 100 80 60 6400mm 2 1000mm 2 500mm 2 100mm 2 25mm 2 JEDEC TJ MAX 20 0 0 0.2 0.4 0.6 0.8 1.0 1.2 TOTAL POWER DISSIPATION (W) 500mm 2 40 300mm 2 100mm 2 20 25mm 2 JEDEC 120 JUNCTION TEMPERATURE, TJ (°C) 120 100 80 60 6400mm 2 1000mm 2 500mm 2 100mm 2 25mm 2 JEDEC TJ MAX 0 0 0.2 0.4 0.6 0.8 1.0 1.2 TOTAL POWER DISSIPATION (W) Figure 89. Junction Temperature vs.
PAGE 26
ADP7182 Data Sheet Thermal Characterization Parameter, ΨJB PCB LAYOUT CONSIDERATIONS When the board temperature is known, use the thermal characterization parameter, ΨJB, to estimate the junction temperature rise (see Figure 93 and Figure 94). Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula: Place the input capacitor as close as possible to the VIN and GND pins.
PAGE 27
Data Sheet ADP7182 OUTLINE DIMENSIONS 2.48 2.38 2.23 3.10 3.00 SQ 2.90 8 5 EXPOSED PAD INDEX AREA 4 TOP VIEW 1 BOTTOM VIEW 0.80 MAX 0.55 NOM 0.80 0.75 0.70 SEATING PLANE 0.30 0.25 0.18 1.74 1.64 1.49 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.50 BSC 0.20 MIN PIN 1 INDICATOR (R 0.2) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-05-2013-B 0.50 0.40 0.
PAGE 28
ADP7182 Data Sheet ORDERING GUIDE Model1 ADP7182ACPZ-R7 ADP7182ACPZ-5.0-R7 ADP7182AUJZ-R7 ADP7182AUJZ-1.8-R7 ADP7182AUJZ-2.5-R7 ADP7182AUJZ-3.0-R7 ADP7182AUJZ-5.0-R7 ADP7182UJ-EVALZ ADP7182CP-EVALZ 1 2 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Output Voltage (V)2 Adjustable −5 Adjustable −1.8 −2.