Datasheet

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20 V, 500 mA, Low Noise, CMOS LDO

Data Sheet

ADP7104

Rev. F Document Feedback

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FEATURES

Input voltage range: 3.3 V to 20 V

Maximum output current: 500 mA

Low noise: 15 µV rms for fixed output versions

PSRR performance of 60 dB at 10 kHz, V

OUT

= 3.3 V

Reverse current protection

Low dropout voltage: 350 mV at 500 mA

Initial accuracy: ±0.8%

Accuracy over line, load, and temperature: −2%/+1%

Low quiescent current (V

= 5 V), I

GND

= 900 μA with 500 mA load

Low shutdown current: <40 µA at V

= 12 V, stable with small

1 µF ceramic output capacitor

7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V,

5 V, and 9 V

Adjustable output from 1.22 V to V

− V

Foldback current limit and thermal overload protection

User programmable precision UVLO/enable

Power-good indicator

8-lead LFCSP and 8-lead SOIC packages

APPLICATIONS

Regulation to noise sensitive applications: ADC, DAC circuits,

precision amplifiers, high frequency oscillators, clocks,

and PLLs

Communications and infrastructure

Medical and healthcare

Industrial and instrumentation

TYPICAL APPLICATION CIRCUITS

OUT

= 5V

= 8V

VOUTVIN

GND

SENSE

EN/

UVLO

COUT

1µF

CIN

1µF

OFF

09507-001

RPG

100kΩ

Figure 1. ADP7104 with Fixed Output Voltage, 5 V

OUT

= 5V

= 8V

VOUTVIN

GND

ADJ

EN/

UVLO

COUT

1µF

CIN

1µF

OFF

13kΩ

40.2kΩ

09507-002

RPG

100kΩ

Figure 2. ADP7104 with Adjustable Output Voltage, 5 V

GENERAL DESCRIPTION

The ADP7104 is a CMOS, low dropout linear regulator that oper-

ates from 3.3 V to 20 V and provides up to 500 mA of output

current. This high input voltage LDO is ideal for regulation of

high performance analog and mixed signal circuits operating

from 19 V to 1.22 V rails. Using an advanced proprietary archi-

tecture, it provides high power supply rejection, low noise, and

achieves excellent line and load transient response with just a

small 1 µF ceramic output capacitor.

The ADP7104 is available in seven fixed output voltage options

and an adjustable version, which allows output voltages that range

from 1.22 V to V

− V

via an external feedback divider.

The ADP7104 output noise voltage is 15 μV rms and is inde-

pendent of the output voltage. A digital power-good output

allows power system monitors to check the health of the output

voltage. A user programmable precision undervoltage lockout

function facilitates sequencing of multiple power supplies.

The ADP7104 is available in 8-lead, 3 mm × 3 mm LFCSP

and 8-lead SOIC packages. The LFCSP offers a very compact

solution and also provides excellent thermal performance for

applications requiring up to 500 mA of output current in a

small, low-profile footprint.

Summary of content (28 pages)

PAGE 1
FEATURES TYPICAL APPLICATION CIRCUITS VIN = 8V CIN + 1µF VIN VOUT SENSE ON OFF R1 100kΩ VOUT = 5V + COUT 1µF RPG 100kΩ EN/ UVLO R2 100kΩ PG PG GND 09507-001 Input voltage range: 3.3 V to 20 V Maximum output current: 500 mA Low noise: 15 µV rms for fixed output versions PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V Reverse current protection Low dropout voltage: 350 mV at 500 mA Initial accuracy: ±0.
PAGE 2
ADP7104 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 16 Typical Application Circuits......................................................
PAGE 3
Data Sheet ADP7104 SPECIFICATIONS VIN = (VOUT + 1 V) or 3.3 V (whichever is greater), EN = VIN, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted. Table 1.
PAGE 4
ADP7104 Data Sheet Parameter PROGRAMMABLE EN/UVLO UVLO Threshold Rising UVLO Threshold Falling Symbol Conditions Min Typ Max Unit UVLORISE UVLOFALL 1.18 1.23 1.13 1.28 V V UVLO Hysteresis Current Enable Pull-Down Current Start Threshold Shutdown Threshold Hysteresis OUTPUT NOISE UVLOHYS IEN-IN VSTART VSHUTDOWN 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C, 10 kΩ in series with the enable pin VEN > 1.
PAGE 5
Data Sheet ADP7104 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN to GND VOUT to GND EN/UVLO to GND PG to GND SENSE/ADJ to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating −0.3 V to +22 V −0.3 V to +20 V −0.3 V to VIN −0.3 V to VIN −0.3 V to VOUT −65°C to +150°C −40°C to +125°C JEDEC J-STD-020 Stresses above those listed under absolute maximum ratings may cause permanent damage to the device.
PAGE 6
ADP7104 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 8 VIN GND 3 TOP VIEW (Not to Scale) NC 4 VOUT 1 7 PG SENSE/ADJ 2 5 EN/UVLO NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. IT IS HIGHLY RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE BE CONNECTED TO THE GROUND PLANE ON THE BOARD. ADP7104 8 VIN 7 PG TOP VIEW GND 3 (Not to Scale) 6 GND 5 EN/UVLO NC 4 6 GND NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2.
PAGE 7
Data Sheet ADP7104 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 7.5 V, VOUT = 5 V, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted. 3.35 LOAD = 100µA LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA LOAD = 500mA 1000 GROUND CURRENT (µA) 3.33 3.31 3.29 3.27 800 600 400 200 –40°C –5°C 85°C 25°C 0 09507-005 3.
PAGE 8
ADP7104 120 1200 GROUND CURRENT (µA) 140 SHUTDOWN CURRENT (µA) 1400 3.3V 4.0V 6.0V 8.0V 12.0V 20.0V 100 80 60 40 1000 800 600 400 200 20 –25 0 25 50 75 100 0 3.1 09507-011 0 –50 125 TEMPERATURE (°C) 3.3 3.4 3.5 3.6 3.7 Figure 14. Ground Current vs. Input Voltage (in Dropout) 5.05 VOUT = 3.3V TA = 25°C LOAD = 100µA LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA LOAD = 500mA 5.04 300 5.03 250 5.02 200 VOUT (V) DROPOUT (mV) 3.2 VIN (V) Figure 11. Shutdown Current vs.
PAGE 9
Data Sheet 5.05 ADP7104 300 LOAD = 100µA LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA LOAD = 500mA 5.04 5.03 250 5.02 200 DROPOUT (mV) VOUT (V) VOUT = 5V TA = 25°C 5.01 5.00 4.99 150 100 4.98 4.97 50 6 8 10 12 14 16 20 18 VIN (V) 0 09507-017 1000 Figure 20. Dropout Voltage vs. Load Current, VOUT = 5 V 1000 5.05 LOAD = 100µA LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 900 800 5.00 4.95 4.90 600 4.85 VOUT (V) 700 500 400 4.80 4.75 4.70 200 4.65 100 4.
PAGE 10
ADP7104 1.85 900 LOAD = 100µA LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA LOAD = 500mA 800 700 GROUND CURRENT (µA) 1.83 VOUT (V) Data Sheet 1.81 1.79 LOAD = 100µA LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 600 500 400 300 200 1.77 –40°C –5°C 25°C 85°C 0 09507-021 1.75 125°C TJ (°C) –40°C –5°C 25°C 85°C 09507-126 100 125°C TJ (°C) Figure 23. Output Voltage vs. Junction Temperature, VOUT = 1.8 V Figure 26. Ground Current vs. Junction Temperature, VOUT = 1.8 V 1.
PAGE 11
Data Sheet 5.07 5.06 2.0 LOAD = 100µA LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA LOAD = 500mA IOUT SHUTDOWN CURRENT (µA) 5.08 ADP7104 VOUT (V) 5.05 5.04 5.03 5.02 5.01 5.00 1.5 3.3V 4V 5V 6V 8V 10V 12V 15V 18V 20V 1.0 0.5 –5°C 25°C 85°C 125°C TJ (°C) 0 5.07 –10 5.06 –20 5.05 –30 5.04 –40 5.02 5.00 –80 4.
PAGE 12
ADP7104 –20 –30 –30 –40 –40 PSRR (dB) –50 –60 –70 –80 –90 –90 1k 10k 100k 1M 10M 0 –10 –20 –100 10 09507-030 100 Figure 35. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 4.3 V 0 –10 –20 –30 –40 –40 PSRR (dB) –30 –60 –80 –80 –90 –90 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 36. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 3.
PAGE 13
ADP7104 0 0 –10 –10 –20 –20 –30 –30 –40 –40 PSRR (dB) –50 –60 –70 –60 –80 LOAD = 500mA LOAD = 300mA LOAD = 100mA LOAD = 10mA LOAD = 1mA 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 41. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.2 V 0 –10 –20 –100 0 0 PSRR (dB) –30 –50 –60 –50 –70 –80 –80 –90 –90 10k 100k 1M 10M FREQUENCY (Hz) Figure 42. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V Adjustable –20 –100 09507-037 1k 0 0.
PAGE 14
ADP7104 Data Sheet 0 LOAD = 500mA LOAD = 300mA LOAD = 100mA LOAD = 10mA LOAD = 1mA –10 –20 LOAD CURRENT 1 –30 PSRR (dB) –40 –50 –60 OUTPUT VOLTAGE 2 –70 –80 0 0.25 0.50 0.75 1.00 1.25 09507-042 –100 1.50 HEADROOM VOLTAGE (V) Figure 47. Power Supply Rejection Ratio vs. Headroom Voltage, 100 kHz, VOUT = 5 V CH1 500mA Ω B W CH2 50mV B W M 20µs T 10% A CH1 270mA 09507-045 –90 Figure 50. Load Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA to 500 mA, VOUT = 1.
PAGE 15
Data Sheet ADP7104 INPUT VOLTAGE INPUT VOLTAGE OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 2 B W CH2 10mV B W M 4µs T 9.8% A CH4 1.56V 09507-048 CH1 1V CH1 1V B W CH2 10mV B W M 4µs T 9.8% A CH4 1.56V 09507-051 1 1 Figure 53. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 500 mA, VOUT = 1.8 V Figure 56. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA, VOUT = 1.8 V INPUT VOLTAGE INPUT VOLTAGE OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 2 B W CH2 10mV B W M 4µs T 9.8% A CH4 1.
PAGE 16
ADP7104 Data Sheet THEORY OF OPERATION The ADP7104 is a low quiescent current, low-dropout linear regulator that operates from 3.3 V to 20 V and provides up to 500 mA of output current. Drawing a low 1 mA of quiescent current (typical) at full load makes the ADP7104 ideal for battery-operated portable equipment. Typical shutdown current consumption is 40 μA at room temperature. Optimized for use with small 1 µF ceramic capacitors, the ADP7104 provides excellent transient performance.
PAGE 17
Data Sheet ADP7104 APPLICATIONS INFORMATION Output Capacitor The ADP7104 is designed for operation with small, space-saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 1 µF capacitance with an ESR of 1 Ω or less is recommended to ensure the stability of the ADP7104.
PAGE 18
ADP7104 Data Sheet The ADP7104 uses the EN/UVLO pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 64, when a rising voltage on EN crosses the upper threshold, VOUT turns on. When a falling voltage on EN/ UVLO crosses the lower threshold, VOUT turns off. The hysteresis of the EN/UVLO threshold is determined by the Thevenin equivalent resistance in series with the EN/UVLO pin. Hysteresis can also be achieved by connecting a resistor in series with EN/UVLO pin.
PAGE 19
Data Sheet ADP7104 POWER-GOOD FEATURE NOISE REDUCTION OF THE ADJUSTABLE ADP7104 The ADP7104 provides a power-good pin (PG) to indicate the status of the output. This open-drain output requires an external pull-up resistor to VIN. If the part is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below 90% of the nominal output voltage, the power-good pin (PG) immediately transitions low. During soft-start, the rising threshold of the power-good signal is 93.
PAGE 20
ADP7104 Data Sheet CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION The ADP7104 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP7104 is designed to current limit when the output load reaches 600 mA (typical). When the output load exceeds 600 mA, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is included, which limits the junction temperature to a maximum of 150°C (typical).
PAGE 21
ADP7104 145 135 135 125 125 115 105 95 85 75 65 55 6400mm 2 500mm 2 25mm 2 TJ MAX 45 35 0.2 0.6 0.4 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 TOTAL POWER DISSIPATION (W) 85 75 65 55 6400mm 2 500mm 2 25mm 2 TJ MAX 45 35 25 0 0.2 0.4 0.6 140 130 130 JUNCTION TEMPERATURE (°C) 140 120 110 100 90 80 70 6400mm 2 500mm 2 25mm 2 TJ MAX 60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 70 6400mm 2 500mm 2 25mm 2 TJ MAX 50 0 0.2 0.
PAGE 22
ADP7104 Data Sheet 140 In the case where the board temperature is known, use the thermal characterization parameter, ΨJB, to estimate the junction temperature rise (see Figure 76 and Figure 77). Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula: (5) The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP package and 31.3°C/W for the 8-lead SOIC package.
PAGE 23
Data Sheet ADP7104 PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP7104. However, as listed in Table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. 09507-074 Place the input capacitor as close as possible to the VIN and GND pins.
PAGE 24
ADP7104 Data Sheet OUTLINE DIMENSIONS 2.48 2.38 2.23 3.10 3.00 SQ 2.90 8 5 EXPOSED PAD INDEX AREA 4 TOP VIEW SEATING PLANE 0.30 0.25 0.18 0.20 MIN PIN 1 INDICATOR (R 0.2) 1 BOTTOM VIEW 0.80 MAX 0.55 NOM 0.80 0.75 0.70 1.74 1.64 1.49 0.50 BSC 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-05-2013-B 0.50 0.40 0.
PAGE 25
Data Sheet ADP7104 ORDERING GUIDE Model 1 ADP7104ACPZ-R7 ADP7104ACPZ-1.5-R7 ADP7104ACPZ-1.8-R7 ADP7104ACPZ-2.5-R7 ADP7104ACPZ-3.0-R7 ADP7104ACPZ-3.3-R7 ADP7104ACPZ-5.0-R7 ADP7104ACPZ-9.0-R7 ADP7104ARDZ-R7 ADP7104ARDZ-1.5-R7 ADP7104ARDZ-1.8-R7 ADP7104ARDZ-2.5-R7 ADP7104ARDZ-3.0-R7 ADP7104ARDZ-3.3-R7 ADP7104ARDZ-5.0-R7 ADP7104ARDZ-9.
PAGE 26
ADP7104 Data Sheet NOTES Rev.
PAGE 27
Data Sheet ADP7104 NOTES Rev.