Datasheet

ADP7102 Data Sheet
Rev. C | Page 20 of 28
POWER GOOD FEATURE
The ADP7102 provides a power good pin (PG) to indicate
the status of the output. This open-drain output requires an
external pull-up resistor to VIN. If the part is in shutdown
mode, current-limit mode, or thermal shutdown, or if it falls
below 90% of the nominal output voltage, the power-good pin
(PG) immediately transitions low. During soft-start, the rising
threshold of the power-good signal is 93.5% of the nominal
output voltage.
The open-drain output is held low when the ADP7102 has
sufficient input voltage to turn on the internal PG transistor.
The PG transistor is terminated via a pull-up resistor to VOUT
or VIN.
Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90% trip point when
this voltage is falling. Regulator input voltage brownouts or
glitches trigger power no good signals if V
OUT
falls below 90%.
A normal power-down causes the power good signal to go low
when V
OUT
drops below 90%.
Figure 68 and Figure 69 show the typical power good rising and
falling threshold over temperature.
0
1
2
3
4
5
6
4.2 4.3 4.4 4.5 4.6
4.7 4.8 4.9 5.0
PG (V)
V
OUT
(V)
PG –40
°C
PG –
5
°C
PG +2
5°C
PG +85
°C
PG +12
5
°C
09506-063
Figure 68. Typical Power Good Threshold vs. Temperature, V
OUT
Rising
0
1
2
3
4
5
6
4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0
PG (V)
V
OUT
(V)
PG –40°C
PG –5°C
PG +25°C
PG +85°C
PG +125°C
09506-064
Figure 69. Typical Power Good Threshold vs. Temperature, V
OUT
Falling
NOISE REDUCTION OF THE ADJUSTABLE
ADP7102
The ultralow output noise of the fixed output ADP7102 is
achieved by keeping the LDO error amplifier in unity gain
and setting the reference voltage equal to the output voltage.
This architecture does not work for an adjustable output
voltage LDO. The adjustable output ADP7102 uses the more
conventional architecture where the reference voltage is fixed
and the error amplifier gain is a function of the output voltage.
The disadvantage of the conventional LDO architecture is that
the output voltage noise is proportional to the output voltage.
The adjustable LDO circuit may be modified slightly to
reduce the output voltage noise to levels close to that of the
fixed output ADP7102. The circuit shown in Figure 70 adds
two additional components to the output voltage setting resistor
divider. C
NR
and R
NR
are added in parallel with R
FB1
to reduce
the ac gain of the error amplifier. R
NR
is chosen to be equal to
R
FB2
; this limits the ac gain of the error amplifier to approxi-
mately 6 dB. The actual gain is the parallel combination of R
NR
and R
FB1
, divided by R
FB2
. This ensures that the error amplifier
always operates at greater than unity gain.
C
NR
is chosen by setting the reactance of C
NR
equal to R
FB1
−
R
NR
at a frequency between 50 Hz and 100 Hz. This sets the
frequency where the ac gain of the error amplifier is 3 dB
down from its dc gain.
VOUT = 5V
VIN = 8V
PG
VOUTVIN
PG
GND
ADJ
EN/
UVLO
100kΩ
100kΩ
100kΩ
COUT
1µF
CIN
1µF
ON
OFF
R
NR
13kΩ
R
FB2
13kΩ
++
R
FB1
40.2kΩ
C
NR
100nF
+
09506-065
Figure 70. Noise Reduction Modification to Adjustable LDO
The noise of the adjustable LDO can be found by using the
following formula, assuming the noise of a fixed output LDO is
approximately 15 μ V.
















Ω+
+×
kΩ13/
k2.40
/1k
Ω13/
1
1
1μV
15
Based on the component values shown in Figure 70, the
ADP7102 has the following characteristics:
• DC gain of 4.09 (12.2 dB)
• 3 dB roll off frequency of 59 Hz
• High frequency ac gain of 1.76 (4.89 dB)
• Noise reduction factor of 1.33 (2.59 dB)
• RMS noise of the adjustable LDO without noise reduction
of 27.8 µV rms
• RMS noise of the adjustable LDO with noise reduc-
tion (assuming 15 µV rms for fixed voltage option) of
19.95 µV rms