Datasheet

Data Sheet ADP7102
Rev. C | Page 19 of 28
PROGRAMABLE UNDERVOLTAGE LOCKOUT (UVLO)
The ADP7102 uses the EN/UVLO pin to enable and disable
the VOUT pin under normal operating conditions. As shown
in Figure 65, when a rising voltage on EN crosses the upper
threshold, VOUT turns on. When a falling voltage on EN/
UVLO crosses the lower threshold, VOUT turns off. The
hysteresis of the EN/UVLO threshold is determined by
the Thevenin equivalent resistance in series with the EN/
UVLO pin.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.001.00
0
V
OUT
, EN RISE
V
OUT
, EN FALL
09506-060
Figure 65. Typical V
OUT
Response to EN Pin Operation
The upper and lower thresholds are user programmable and
can be set using two resistors. When the EN/UVLO pin voltage
is below 1.22 V, the LDO is disabled. When the EN/UVLO pin
voltage transitions above 1.22 V, the LDO is enabled and 10 µA
hysteresis current is sourced out of the pin raising the voltage,
thus providing threshold hysteresis. Typically, two external
resistors program the minimum operational voltage for the LDO.
The resistance values, R1 and R2 can be determined from:
R1 = V
HYS
/10 μA
R2 = 1.22 V × R1/(V
IN
− 1.22 V)
where:
V
IN
is the desired turn-on voltage.
V
HYS
is the desired EN/UVLO hysteresis level.
Hysteresis can also be achieved by connecting a resistor in series
with EN/UVLO pin. For the example shown in Figure 66, the
enable threshold is 2.44 V with a hysteresis of 1 V.
VOUT = 5V
VIN = 8V
PG
VOUT
VIN
PG
GND
SENSE
EN/
UVLO
RPG
100kΩ
R2
100kΩ
R1
100k
Ω
COUT
1µF
CIN
1µF
ON
OFF
+
+
09506-061
Figure 66. Typical EN Pin Voltage Divider
Figure 65 shows the typical hysteresis of the EN/UVLO pin.
This prevents on/off oscillations that can occur due to noise
on the EN pin as it passes through the threshold points.
The ADP7102 uses an internal soft-start to limit the inrush
current when the output is enabled. The start-up time for the
3.3 V option is approximately 580 μs from the time the EN
active threshold is crossed to when the output reaches 90%
of its final value. As shown in Figure 67, the start-up time is
dependent on the output voltage setting.
TIME (µs)
0
500 1000 1500
2000
6
4
5
3
2
1
0
V
OUT
(V)
5V
3.3V
ENABLE
09506-062
Figure 67. Typical Start-Up Behavior