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Keypad Decoder and I/O Expansion

Data Sheet

ADP5589

Rev. B Document Feedback

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FEATURES

16-element FIFO for event recording

19 configurable I/Os allowing functions such as

Keypad decoding for matrix up to 11 × 8

Key press/release interrupts

Key pad lock/unlock

GPIO functions

GPI with selectable interrupt level

100 kΩ or 300 kΩ pull-up resistors

300 kΩ pull-down resistors

GPO with push-pull or open drain

Dual programmable logic blocks

PWM generator

Internal PWM generation

External PWM with internal PWM AND function

Clock divider

Reset generators

C interface with fast-mode plus (Fm+) support up to 1 MHz

Open-drain interrupt output

24-lead LFCSP 3.5 mm × 3.5 mm

25-ball WLCSP 1.99 mm × 1.99 mm

APPLICATIONS

Devices requiring keypad entry and I/O expansion

capabilities

FUNCTIONAL BLOCK DIAGRAM

SDA

GPI SCAN

AND

DECODE

UVLO

POR

C INTERFACE

OSCILLATOR

REGISTERS

KEY SCAN

AND

DECODE

LOGIC 1

I/O

CONFIG

INT

RST

LOGIC 2

CLK DIV

PWM

SCL

VDD

ADP5589

GND

RESET 1

GEN

RESET 2

GEN

09714-001

C10

Figure 1.

GENERAL DESCRIPTION

The ADP5589 is a 19 I/O port expander with built-in keypad

matrix decoder, programmable logic, reset generator, and

PWM generator. I/O expander ICs are used in portable devices

(phones, remote controls, and cameras) and nonportable

applications (healthcare, industrial, and instrumentation). I/O

expanders can be used to increase the number of I/Os available

to a processor or to reduce the number of I/Os required

through interface connectors for front panel designs.

The ADP5589, which handles all key scanning and decoding,

can flag the main processor via an interrupt line when new key

events have occurred. In addition, GPI changes and logic

changes can be tracked as events via the FIFO, eliminating the

need to monitor different registers for event changes. The

ADP5589 is equipped with a FIFO to store up to 16 events.

Events can be read back by the processor via an I

C compatible

interface.

The ADP5589 frees up the main processor from having to

monitor the keypad, thereby reducing power consumption

and/or increasing processor bandwidth for performing other

functions.

The programmable logic functions allow common logic

requirements to be integrated as part of the GPIO expander,

saving board area and cost.

Summary of content (52 pages)

PAGE 1
Keypad Decoder and I/O Expansion ADP5589 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM 16-element FIFO for event recording 19 configurable I/Os allowing functions such as Keypad decoding for matrix up to 11 × 8 Key press/release interrupts Key pad lock/unlock GPIO functions GPI with selectable interrupt level 100 kΩ or 300 kΩ pull-up resistors 300 kΩ pull-down resistors GPO with push-pull or open drain Dual programmable logic blocks PWM generator Internal PWM generation External PWM with internal PWM AND
PAGE 2
ADP5589 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Event FIFO .....................................................................................9 Applications ....................................................................................... 1 Key Scan Control ...........................................................................9 Functional Block Diagram ...........................................
PAGE 3
Data Sheet ADP5589 SPECIFICATIONS VDD = 1.8 V to 3.3 V, TA = −40°C to +85⁰C, unless otherwise noted. 1 Table 1.
PAGE 4
ADP5589 Data Sheet Parameter Hold Time for Start/Repeated Start Bus Free Time for Stop and Start Condition Setup Time for Stop Condition Data Valid Time Data Valid Acknowledge Rise Time for SCL and SDA Fall Time for SCL and SDA Pulse Width of Suppressed Spike Capacitive Load for Each Bus Line Symbol tHD; STA tBUF tSU; STO tVD; DAT tVD; ACK tR tF tSP CB 6 Test Conditions/Comments Min 0.26 0.5 0.26 Typ Max 0.45 0.
PAGE 5
Data Sheet ADP5589 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VDD to Ground SCL, SDA, RST, INT, R0, R1, R2, R3, R4, R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10 to Ground Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Soldering Conditions 1 θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating –0.3 V to 4 V –0.3 V to (VDD + 0.3 V) Table 3.
PAGE 6
ADP5589 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS R7 1 18 VDD R6 2 17 RST R5 3 ADP5589 16 C7 R4 4 TOP VIEW (Not to Scale) 15 C6 R3 5 14 C5 R2 6 09714-003 C3 12 C2 11 9 C0 C1 10 R0 8 R1 7 13 C4 1 2 3 4 5 A VDD SDA SCL GND C10 B R0 INT RST C0 C9 C R2 R1 C1 C2 C8 D R4 R3 C3 C4 C7 E R5 R6 R7 C5 C6 TOP VIEW (BALL SIDE DOWN) Not to Scale NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 3.
PAGE 7
Data Sheet ADP5589 QUICK DEVICE OVERVIEW VDD GND ADP5589 UVLO POR RST OSCILLATOR SDA I2C INTERFACE INT SCL (R0) (R1) (R2) (R3) (R4) (R5) (R6) (R7) (C0) (C1) (C2) (C3) (C4) (C5) (C6) (C7) (C8) (C9) (C10) R0 R1 R2 R3 R4 R5 R6 R7 C0 C1 C2 C3 C4 I/O CONFIGURATION ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 COL 0 COL 1 COL 2 COL 3 COL 4 COL 5 COL 6 COL 7 COL 8 COL 9 COL 10 (R0) (R1) (R2) (R3) (R4) (R5) (R6) (R7) (C0) (C1) (C2) (C3) (C4) (C5) (C6) (C7) (C8) (C9) (C10) GPIO 1 GPIO 2 GPIO 3 GPIO
PAGE 8
ADP5589 Data Sheet DEVICE ENABLE When sufficient voltage is applied to VDD and the RST pin is driven with a logic high level, the ADP5589 starts up in standby mode with all settings at default. The user can configure the device via the I2C interface. When the RST pin is low, the ADP5589 enters a reset state and all settings return to default. The RST pin features a debounce filter. DEVICE OVERVIEW The ADP5589 contains 19 multiconfigurable input/output pins.
PAGE 9
Data Sheet ADP5589 DETAILED DESCRIPTION EVENT FIFO EC = 3 FIRST READ It is important to understand the function of the event FIFO. The ADP5589 features an event FIFO that can record as many as 16 events. By default, the FIFO primarily records key events, such as key press and key release. However, it is possible to configure the general-purpose input (GPI) and logic activity to generate event information on the FIFO as well.
PAGE 10
ADP5589 Data Sheet scanned; therefore, if multiple keys are pressed, they are detected. VDD To prevent glitches or narrow press times being registered as a valid key press, the key scanner requires the key be pressed for two scan cycles. The key scanner has a wait time between each scan cycle; therefore, the key must be pressed and held for at least this wait time to register as being pressed. If the key is continuously pressed, the key scanner continues to scan, wait, scan, wait, and so forth.
PAGE 11
Data Sheet ADP5589 PIN_CONFIG_A[7:0] PIN_CONFIG_B[7:0] PIN_CONFIG_C[2:0] RESET_TRIGGER_TIME[2:0] RESET1_EVENT_A[7:0] RESET1_EVENT_B[7:0] RESET1_EVENT_C[7:0] RESET2_EVENT_A[7:0] RESET2_EVENT_B[7:0] LOCK_EN EXT_LOCK_EVENT[7:0] UNLOCK1[7:0] UNLOCK2[7:0] UNLOCK_TIMER[2:0] INT_MASK_TIMER[4:0] RESET 1_INITIATE RESET 2_INITIATE LOCK_STAT LOCK_INT EVENT_INT KEY SCAN CONTROL OVRFLOW_INT I2C BUSY? KEY EVENT GPI EVENT EC[4:0] FIFO UPDATE LOGIC EVENT FIFO COLUMN SINK ON/OFF ROW SENSE I/O CONFIGURATION 89 1
PAGE 12
ADP5589 Data Sheet COL0 KEY 32 KEY SCAN COL1 COL2 PRESS PRESS GHOST PRESS ROW0 EVENT_INT CLEARED EVENT_INT FIFO 1 32 0 0 0 0 0 0 FIFO READ FIFO 0 0 0 0 0 0 0 0 ROW1 1 FIFO KEY 32 RELEASE 0 32 0 0 0 0 0 0 ROW2 Figure 13. Asserting the EVENT_INT Interrupt Figure 14. COL0-ROW3 is a Ghost Key Due to Short Between ROW0, COL0, COL2 and ROW3 During Key Press Key Pad Extension As shown in Figure 11, the keypad can be extended if each row is connected directly to ground by a switch.
PAGE 13
Data Sheet ADP5589 When full unlock is achieved, FIFO and event count updates resume. Note that if a key press is used as the second unlock event, the release of that key is captured on the FIFO after unlocking is completed. The ADP5589 features an unlock timer, UNLOCK_TIMER[2:0] (0x36[2:0]). When enabled, after the first unlock event occurs, the unlock timer begins counting, and the second unlock event must occur before the unlock timer expires.
PAGE 14
ADP5589 Data Sheet LOCKED LOCK_STAT = 1 EVENT DETECTED? NO YES MASK TIMER ENABLED? YES YES SET EVENT_INT = 1 MASK TIMER EXPIRED? NO NO START MASK TIMER FIRST UNLOCK EVENT? NO YES LOCK_STAT = 1 NO SECOND UNLOCK EVENT REQUIRED? YES NO UNLOCK TIMER ENABLED? YES EVENT DETECTED? NO START UNLOCK TIMER YES YES SET EVENT_INT = 1 YES EVENT DETECTED? MASK TIMER ENABLED? MASK TIMER EXPIRED? NO NO YES NO YES MASK TIMER ENABLED? START MASK TIMER SET EVENT_INT = 1 YES MASK NO TIMER EXP
PAGE 15
Data Sheet ADP5589 GPI 6 GPI Input GPI_INT_LEVEL_A[5] GPI_INTERRUPT_EN_A[5] GPI_STATUS_A[5] CLEARED BY READ GPI_INT_STAT_A[5] PIN_CONFIG_A[7:0] PIN_CONFIG_B[7:0] CLEARED BY WRITE ‘1’ GPI_INT PIN_CONFIG_C[2:0] Figure 18. Single GPI Example LOCK_EN EXT_LOCK_EVENT[7:0] LOCK_STAT GPIs can be programmed to generate FIFO events via the GPI_EVENT_EN_x registers. GPIs in this mode do not generate GPI_INT interrupts and instead generate EVENT_INT interrupts.
PAGE 16
ADP5589 Data Sheet LOGIC BLOCKS The outputs from the logic blocks can be configured to generate interrupts. They can also be configured to generate events on the FIFO. The LCK_TRK_LOGIC (0x4D[4]) bit can be used to allow logic events (programmed for FIFO updating) to be tracked when the keypad is locked. Several of the ADP5589 I/O lines can be used as inputs and outputs for implementing some common logic functions.
PAGE 17
Data Sheet ADP5589 LA2 (LY1) LA2 0 OUT LY1 1 LA2 SEL OUT 1 SEL (IN_LY1) IN_LA2 LA2_INV IN_LB2 (LY1) LY1_CASCADE (IN_LY1) IN_LA2 0 AND 0 AND IN_LC2 LB2 LB2 LB2 0 1 OUT IN_LB2 SEL LC2 LC2 0 1 OUT OR 0 OR IN_LC2 IN_LC2 SEL LC2_INV (IN_LY1) IN_LA2 OUT AND2 SEL MUX GND IN_LB2 LB2_INV LC2 (IN_LY1) IN_LA2 1 1 OUT AND2 OR2 OR2 SEL XOR2 FF2 XOR 0 IN_LB2 XOR IN_LC2 1 OUT XOR2 IN_LA2 IN_LB2 SEL IN_LC2 000 001 010 LY2 011 OUT 100 0 LY2 1 OUT LY2 SEL 10
PAGE 18
ADP5589 Data Sheet INTERRUPTS RST RST_PASSTHRU_EN KEY SCAN CONTROL GPI SCAN CONTROL The INT pin can be asserted low if any of the internal interrupt sources is active. The user can select which internal interrupts interact with the external interrupt pin in register INT_EN (Address 0x4E, Bits[7:0]) (refer to Table 86).
PAGE 19
Data Sheet ADP5589 REGISTER INTERFACE Register access of the ADP5589 is acquired via its I2C-compatible serial interface. The interface can support clock frequencies of up to 1 MHz. If the user is accessing the FIFO or key event counter (KEC), FIFO/KEC updates are paused. If the clock frequency is very low, events may not be recorded in a timely manner. FIFO or KEC updates can happen up to 23 μs after an interrupt is asserted because of the number of I2C cycles required to perform an I2C read or write.
PAGE 20
ADP5589 Data Sheet followed by the R/W bit set to 1 for a read cycle. The ADP5589 acknowledges the address byte by pulling the data line low. The 8-bit data is then read. The address pointer is then incremented to read the next data byte, and the host continues to pull the data line low for each byte (master acknowledge) until the n data byte is read. The host pulls the data line high (no acknowledge) after the last byte is read, and a stop condition completes the sequence.
PAGE 21
Data Sheet ADP5589 REGISTER MAP Table 6. Addr.
PAGE 22
ADP5589 Data Sheet Addr.
PAGE 23
Data Sheet ADP5589 DETAILED REGISTER DESCRIPTIONS Note: N/A throughout this section means not applicable. Note: All registers default to 0000 0000 unless otherwise specified. ID Register 0x00 Table 7. ID Bit Descriptions Bits Name [7: 4] MAN_ID [3:0] REV_ID Default = 0001 XXXX R/W R R Description Manufacturer ID, default = 0001. Rev ID. INT_STATUS Register 0x01 Table 8.
PAGE 24
ADP5589 Data Sheet FIFO_1 Register 0x03 Table 10. FIFO_1 Bit Descriptions Bits 7 Name Event1_State R/W R [6:0] EVENT1_IDENTIFIER[6:0] Description The seven lower bits of each FIFO location contain the event identifier, which can be decoded to reveal the event recorded. Table 11 outlines each event number, what it represents, and the I/O pins associated with it. Bit 7 is the Event 1 state. This bit represents the state of the event that is recorded in EVENT1_IDENTIFIER[6:0].
PAGE 25
Data Sheet ADP5589 FIFO_2 Register 0x04 Table 12. FIFO_2 Bit Descriptions Bits 7 [6:0] Name Event2_State EVENT2_IDENTIFIER[6:0] R/W R R Description Refer to Table 10. Refer to Table 10. FIFO_3 Register 0x05 Table 13. FIFO_3 Bit Descriptions Bits 7 [6: 0] Name Event3_State EVENT3_IDENTIFIER[6:0] R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10.
PAGE 26
ADP5589 Data Sheet FIFO_10 Register 0x0C Table 20. FIFO_10 Bit Descriptions Bits 7 [6:0] Name Event10_State EVENT10_IDENTIFIER[6:0] R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10. R/W R R Description Refer to Table 10. Refer to Table 10.
PAGE 27
Data Sheet ADP5589 GPI_INT_STAT_A Register 0x13 Table 27. GPI_INT_STAT_A Bit Descriptions Bits 7 Name GPI_8_INT R/W R 6 GPI_7_INT R 5 GPI_6_INT R 4 GPI_5_INT R 3 GPI_4_INT R 2 GPI_3_INT R 1 GPI_2_INT R 0 GPI_1_INT R Description 0 = no interrupt. 1 = interrupt due to GPI_8 (R7 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_7 (R6 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_6 (R5 pin). Cleared on read. 0 = no interrupt.
PAGE 28
ADP5589 Data Sheet GPI_STATUS_A Register 0x16 Table 30. GPI_STATUS_A Bit Descriptions Bits 7 Name GPI_8_STAT R/W R 6 GPI_7_STAT R 5 GPI_6_STAT R 4 GPI_5_STAT R 3 GPI_4_STAT R 2 GPI_3_STAT R 1 GPI_2_STAT R 0 GPI_1_STAT R Description 0 = GPI_8 (R7 pin) is low. 1 = GPI_8 (R7 pin) is high. 0 = GPI_7 (R6 pin) is low. 1 = GPI_7 (R6 pin) is high. 0 = GPI_6 (R5 pin) is low. 1 = GPI_6 (R5 pin) is high. 0 = GPI_5 (R4 pin) is low. 1 = GPI_5 (R4 pin) is high. 0 = GPI_4 (R3 pin) is low.
PAGE 29
Data Sheet ADP5589 RPULL_CONFIG_A Register 0x19 Table 33. RPULL_CONFIG_A Bit Descriptions Bits [7:6] Name R3_PULL_CFG R/W R/W Description 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [5:4] R2_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [3:2] R1_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down.
PAGE 30
ADP5589 Data Sheet RPULL_CONFIG_C Register 0x1B Table 35. RPULL_CONFIG_C Bit Descriptions Bits [7 :6] Name C3_PULL_CFG R/W R/W [5: 4] C2_PULL_CFG R/W [3: 2] C1_PULL_CFG R/W [1: 0] C0_PULL_CFG R/W Description 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors.
PAGE 31
Data Sheet ADP5589 RPULL_CONFIG_E Register 0x1D Table 37. RPULL_CONFIG_E Bit Descriptions Bits [7: 6] [5:4] Name R/W Description Reserved. C10_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [3: 2] C9_PULL_CFG R/W 00 = enable 300 kΩ pull-up. 01 = enable 300 kΩ pull-down. 10 = enable 100 kΩ pull-up. 11 = disable all pull-up/pull-down resistors. [1: 0] C8_PULL_CFG R/W 00 = enable 300 kΩ pull-up.
PAGE 32
ADP5589 Data Sheet GPI_INT_LEVEL_B Register 0x1F Table 39. GPI_INT_LEVEL_B Bit Descriptions Bits 7 Name GPI_16_INT_LEVEL R/W R/W 6 GPI_15_INT_LEVEL R/W 5 GPI_14_INT_LEVEL R/W 4 GPI_13_INT_LEVEL R/W 3 GPI_12_INT_LEVEL R/W 2 GPI_11_INT_LEVEL R/W 1 GPI_10_INT_LEVEL R/W 0 GPI_9_INT_LEVEL R/W Description 0 = GPI_16 interrupt is active low. 1 = GPI_16 interrupt is active high. 0 = GPI_15 interrupt is active low. 1 = GPI_15 interrupt is active high. 0 = GPI_14 interrupt is active low.
PAGE 33
Data Sheet ADP5589 GPI_EVENT_EN_B Register 0x22 Table 42. GPI_EVENT_EN_B Bit Descriptions Bits 7 Name GPI_16_EVENT_EN R/W R/W 6 GPI_15_EVENT_EN R/W 5 GPI_14_EVENT_EN R/W 4 GPI_13_EVENT_EN R/W 3 GPI_12_EVENT_EN R/W 2 GPI_11_EVENT_EN R/W 1 GPI_10_EVENT_EN R/W 0 GPI_9_EVENT_EN R/W Description 0 = disable GPI events. 1 = allow GPI 16 activity to generate events on the FIFO. 0 = disable GPI events. 1 = allow GPI 15 activity to generate events on the FIFO. 0 = disable GPI events.
PAGE 34
ADP5589 0 GPI_1_INT_EN Data Sheet R/W 0 = GPI_1_INT is disable. 1 = GPI_1_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_2_INT is set and the GPI interrupt condition is met. GPI_INTERRUPT_EN_B Register 0x25 Table 45. GPI_INTERRUPT_EN_B Bit Descriptions Bits 7 Name GPI_16_INT_EN R/W R/W 6 GPI_15_INT_EN R/W 5 GPI_14_INT_EN R/W 4 GPI_13_INT_EN R/W 3 GPI_12_INT_EN R/W 2 GPI_11_INT_EN R/W 1 GPI_10_INT_EN R/W 0 GPI_9_INT_EN R/W Description 0 = GPI_16_INT is disabled.
PAGE 35
Data Sheet ADP5589 DEBOUNCE_DIS_A Register 0x27 Table 47. DEBOUNCE_DIS_A Bit Descriptions Bits 7 Name GPI_8_DEB_DIS R/W R/W 6 GPI_7_DEB_DIS R/W 5 GPI_6_DEB_DIS R/W 4 GPI_5_DEB_DIS R/W 3 GPI_4_DEB_DIS R/W 2 GPI_3_DEB_DIS R/W 1 GPI_2_DEB_DIS R/W 0 GPI_1_DEB_DIS R/W Description 0 = debounce enabled on GPI 8. 1 = debounce disabled on GPI 8. 0 = debounce enabled on GPI 7. 1 = debounce disabled on GPI 7. 0 = debounce enabled on GPI 6. 1 = debounce disabled on GPI 6.
PAGE 36
ADP5589 Data Sheet DEBOUNCE_DIS_C Register 0x29 Table 49. DEBOUNCE_DIS_C Bit Descriptions Bits [7:3] 2 Name R/W GPI_19_DEB_DIS R/W 1 GPI_18_DEB_DIS R/W 0 GPI_17_DEB_DIS R/W Description Reserved. 0 = debounce enabled on GPI 19. 1 = debounce disabled on GPI 19. 0 = debounce enabled on GPI 18. 1 = debounce disabled on GPI 18. 0 = debounce enabled on GPI 17. 1 = debounce disabled on GPI 17. GPO_DATA_OUT_A Register 0x2A Table 50.
PAGE 37
Data Sheet ADP5589 GPO_DATA_OUT_C Register 0x2C Table 52. GPO_DATA_OUT_C Bit Descriptions Bits [7: 3] 2 Name R/W GPO_19_DATA R/W 1 GPO_18_DATA R/W 0 GPO_17_DATA R/W Description Reserved. 0 = low. 1 = high. 0 = low. 1 = high. 0 = low. 1 = high. GPO_OUT_MODE_A Register 0x2D Table 53.
PAGE 38
ADP5589 Data Sheet GPO_OUT_MODE_C Register 0x2F Table 55. GPO_OUT_MODE_C Bit Descriptions Bits [7: 3] 2 Name R/W GPO_19_DIR R/W 1 GPO_18_DIR R/W 0 GPO_17_DIR R/W Description Reserved. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. GPIO_DIRECTION_A Register 0x30 Table 56.
PAGE 39
Data Sheet ADP5589 GPIO_DIRECTION_C Register 0x32 Table 58. GPIO_DIRECTION_C Bit Descriptions Bits [7:3] 2 Name R/W GPIO_19_DIR R/W 1 GPIO_18_DIR R/W 0 GPIO_17_DIR R/W Description Reserved. 0 = GPIO 19 is an input. 1 = GPIO 19 is an output. 0 = GPIO 18 is an input. 1 = GPIO 18 is an output. 0 = GPIO 17 is an input. 1 = GPIO 17 is an output. UNLOCK1 Register 0x33 Table 59.
PAGE 40
ADP5589 Data Sheet UNLOCK_TIMERS Register 0x36 Table 62. UNLOCK_TIMERS Bit Descriptions Bits [7: 3] Name INT_MASK_TIMER[4:0] R/W R/W [2: 0] UNLOCK_TIMER[2:0] R/W Description If the keypad is locked and this timer is set, any key event (or GPI/logic event programmed to FIFO update) is allowed to generate an EVENT_INT interrupt. This timer then begins counting, and no further events generate an interrupt until this timer has expired (or both unlock events have occurred). 00000 = disabled.
PAGE 41
Data Sheet ADP5589 RESET1_EVENT_C Register 0x3A Table 66. RESET1_EVENT_C Bit Descriptions Bits 7 [6: 0] Name RESET1_EVENT_B Level RESET1_EVENT_C[6:0] R/W R/W R/W Description Defines which level the third reset event should be. Defines an event that can be used to generate the RESET1 signal. RESET2_EVENT_A Register 0x3B Table 67. RESET2_EVENT_A Bit Descriptions Bits 7 Name RESET1_EVENT_B Level R/W R/W [6:0] RESET2_EVENT_A[6:0] R/W Description Defines which level the first reset event should be.
PAGE 42
ADP5589 Bits [1:0] Data Sheet Name RESET_PULSE_WIDTH[1:0] R/W R/W Description Defines the pulse width of the reset signals. Parameter common to both RESET1 and RESET2. 00 = 500 µs. 01 = 1 ms. 10 = 2 ms. 11 = 10 ms. ADP5589AC_Z-00-R7, ADP5589AC_Z-02-R7 Default = 0000 0000 ADP5589AC_Z-01-R7 Default = 0010 0000 PWM_OFFT_LOW Register 0x3E Table 70. PWM_OFFT_LOW Bit Descriptions Bits [7: 0] Name PWM_OFFT_LOW_BYTE[7:0] R/W R/W Description Lower eight bits of PWM off time.
PAGE 43
Data Sheet ADP5589 CLOCK_DIV_CFG Register 0x43 Table 75. CLOCK_DIV_CFG Bit Descriptions Bits 7 6 [5: 1] Name R/W CLK_INV CLK_DIV[4:0] R/W R/W 0 CLK_DIV_EN R/W Description Reserved. Inverts the divided down clock signal. Defines the divide down scale of the externally supplied clock. 00000 = divide by 1 (pass-through). 00001 = divide by 2. 00010 = divide by 3. 00011 = divide by 4. 11111 = divide by 32. Enables the clock divider circuit to divide down the externally supplied clock signal.
PAGE 44
ADP5589 Bits [2: 0] Data Sheet Name LOGIC2_SEL[2:0] R/W R/W Description Configures the digital mux for Logic Block 2. 000 = off/disable. 001 = AND2. 010 = OR2. 011 = XOR2. 100 = FF2. 101 = IN_LA2. 110 = IN_LB2. 111 = IN_LC2. LOGIC_FF_CFG Register 0x46 Table 78. LOGIC_FF_CFG Bit Descriptions Bits [7: 4] 3 Name FF2_SET R/W R/W R/W 2 FF2_CLR R/W 1 FF1_SET R/W 0 FF1_CLR R/W Description Reserved. 0 = FF2 not set in Logic Block 2. 1 = set FF2 in Logic Block 2.
PAGE 45
Data Sheet ADP5589 PIN_CONFIG_A Register 0x49 Table 81. PIN_CONFIG_A Bit Descriptions Bits 7 Name R7_CONFIG R/W R/W 6 R6_CONFIG R/W 5 R5_CONFIG R/W 4 R4_CONFIG R/W 3 R3_CONFIG R/W 2 R2_CONFIG R/W 1 R1_CONFIG R/W 0 R0_CONFIG R/W Description 0 = GPIO 8. 1 = Row 7. 0 = GPIO 7. 1 = Row 6. 0 = GPIO 6. 1 = Row 5. 0 = GPIO 5 (see R4_EXTEND_CFG in PIN_CONFIG_D Register 0x4C Table 84 for alternate configuration, RESET1). 1 = Row 4.
PAGE 46
ADP5589 Data Sheet PIN_CONFIG_D Register 0x4C Table 84. PIN_CONFIG_D Bit Descriptions Bits 7 Name PULL_SELECT R/W R/W Description 0 = 300 kΩ used for row pull-up during key scanning. 1 = 100 kΩ used for row pull-up during key scanning. 6 C4_EXTEND_CFG R/W 0 = C4 remains configured as GPIO 13. 1 = C4 reconfigured as RESET2 output. 5 R4_EXTEND_CFG R/W 0 = R4 remains configured as GPIO 5. 1 = R4 reconfigured as RESET1 output. 4 C6_EXTEND_CFG R/W 0 = C6 remains configured as GPIO 15.
PAGE 47
Data Sheet ADP5589 INT_EN Register 0x4E Table 86. INT_EN Bit Descriptions Bits [7: 6] 5 Name R/W Description Reserved. 0 = Logic 2 interrupt is disabled. 1 = assert the INT pin if LOGIC2_INT is set. LOGIC2_IEN R/W 4 LOGIC1_IEN R/W 0 = Logic 1 interrupt is disabled. 1 = assert the INT pin if LOGIC1_INT is set. 3 LOCK_IEN R/W 0 = lock interrupt is disabled. 1 = assert the INT pin if LOCK_INT is set. 2 OVRFLOW_IEN R/W 0 = overflow interrupt is disabled.
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ADP5589 Data Sheet APPLICATION DIAGRAM VDD INT RST HOST PROCESSOR SCL SDA VDD KP/LOGIC1 OUTPUT/GPI/GPO KP/LOGIC1 INPUT/GPI/GPO SDA KP/LOGIC1 INPUT/GPI/GPO SCL RST VDD ADP5589 KP/LOGIC1 INPUT/GPI/GPO/PWM/CLK KP/RESET1 OUTPUT/GPI/GPO 2 3 4 5 6 7 8 9 10 11 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 OSCILLATOR R0 R1 KEY SCAN AND DECODE
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Data Sheet ADP5589 OUTLINE DIMENSIONS 3.60 3.50 SQ 3.40 PIN 1 INDICATOR 0.25 0.20 0.15 PIN 1 INDICATOR 24 19 18 0.40 BSC 1 EXPOSED PAD 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE 7 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 04-13-2012-A 0.80 0.75 0.70 6 13 12 0.50 0.40 0.30 TOP VIEW 2.30 2.20 SQ 2.10 COMPLIANT TO JEDEC STANDARDS MO-220-WFFE. Figure 32.
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ADP5589 Data Sheet NOTES Rev.
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Data Sheet ADP5589 NOTES Rev.
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ADP5589 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09714-0-1/13(B) Rev.