Datasheet

Data Sheet ADP5588
Rev. C | Page 17 of 28
Table 20. INT_STAT—Register 0x02 (Interrupt Status Register)
Field Bit Description
CMP2_INT 5 Comparator interrupt status. When set, write 1 to clear.
1: Comparator 2 interrupt is detected.
0: Comparator 2 interrupt is not detected.
CMP1_INT 4 Comparator interrupt status. When set, write 1 to clear.
1: Comparator 1 interrupt is detected.
0: Comparator 1 interrupt is not detected.
OVR_FLOW_INT
1
3 Overflow interrupt status. When set, write 1 to clear.
1: Overflow interrupt is detected.
0: Overflow interrupt is not detected.
K_LCK_INT
2
2 Keylock interrupt status. When set, write 1 to clear.
1: Keylock interrupt is detected.
0: Keylock interrupt is not detected.
GPI_INT
1, 3
1 GPI interrupt status. When set, write 1 to clear.
1: GPI interrupt is detected.
0: GPI interrupt is not detected.
KE_INT
1, 3
0 Key events interrupt status. When set, write 1 to clear.
1: Key events interrupt is detected.
0: Key events interrupt is not detected.
1
The KE_INT, GPI_INT, and OVR_FLOW_INT bits reflect the status of the interrupts when the interrupt types are enabled even if the processor interrupt is masked.
2
The K_LCK_INT bit is the interrupt to the processor when the keypad lock sequence is triggered.
3
If there is a pending key event or GPI interrupt in their respective registers, KE_INT does not clear until the FIFO is empty, and the GPI_INT bit does not clear until the
cause of the interrupt is resolved. The host must write a 1 to the INT bits to clear.
Table 21. KEY_LCK_EC_STAT—Register 0x03 (Keylock and Event Counter Register)
Field Bit Description
K_LCK_EN [6] 0: Lock feature is disabled.
1: Lock feature is enabled.
LCK2, LCK1 [5:4] Keypad lock status[1:0] (00 = unlocked; 11 = locked; read only bits).
KEC
1
[3:0]
Key event count of key event register.
1
The KEC bit indicates the key event count of key event registers that have values in the bit (KEC(0000) = 0 events, KEC(0001) = 1 event, KEC(1010) = 10 events. As the
key events are read and cleared, the state machine automatically reduces the event count on KEC.
Table 22. KEY_EVENTx—Register 0x04 to Register 0x0D (Key Event Register A to Key Event Register J)
1
Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
KEY_EVENTA
(Register 0x04)
Key Event Register A status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
KA7 KA6 KA5 KA4 KA3 KA2 KA1 KA0
KEY_EVENTB
(Register 0x05)
Key Event Register B status (KE[6:0] = Key number),
KP[7 ]= 0: released, 1: pressed (cleared on read)
KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0
KEY_EVENTC
(Register 0x06)
Key Event Register C status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
KC7 KC6 KC5 KC4 KC3 KC2 KC1 KC0
KEY_EVENTD
(Register 0x07)
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
KD7 KD6 KD5 KD4 KD3 KD2 Kd1 KD0
KEY_EVENTE
2
(Register 0x08)
Key Event Register B status (KE[6:0] = Key number),
KP[7]= 0: released, 1: pressed (cleared on read)
KE7
KE6
KE5
KE4
KE3
KE2
KE1
KE0
KEY_EVENTF
(Register 0x09)
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
KF7 KF6 KF5 KF4 KF3 KF2 KF1 KF0
KEY_EVENTG
(Register 0x0A)
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
KG7 KG6 KG5 KG4 KG3 KG2 KG1 KG0
KEY_EVENTH
(Register 0x0B)
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
KH7 KH6 KH5 KH4 KH3 KH2 KH1 KH0